Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	261837691	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187353048

1

T1

8

T2

9

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	232401836	1			T1	11		T2	10		T3	1
values[0x0]	103987976	1			T1	5		T2	7		T50	153
values[0x1]	112800927	1			T1	6		T2	3		T50	124

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203270637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

245920102

1

T1

11

T2

11

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1397619	1			T50	2		T53	28		T55	4
valid_sources[0x01]	3831342	1			T50	2		T53	36		T55	3
valid_sources[0x02]	1904850	1			T51	2		T52	2		T53	28
valid_sources[0x03]	2262775	1			T50	4		T51	2		T53	33
valid_sources[0x04]	1411167	1			T50	1		T51	2		T53	37
valid_sources[0x05]	1404337	1			T53	33		T55	4		T67	7
valid_sources[0x06]	1396575	1			T50	4		T53	32		T55	1
valid_sources[0x07]	1400546	1			T50	4		T53	20		T67	4
valid_sources[0x08]	1526006	1			T51	2		T53	32		T55	2
valid_sources[0x09]	1485808	1			T50	5		T53	22		T55	3
valid_sources[0x0a]	1485670	1			T50	2		T51	2		T53	30
valid_sources[0x0b]	2268305	1			T50	1		T51	1		T53	30
valid_sources[0x0c]	1402298	1			T50	1		T52	5		T53	25
valid_sources[0x0d]	1393543	1			T50	1		T53	25		T65	3
valid_sources[0x0e]	1400812	1			T50	4		T51	1		T53	28
valid_sources[0x0f]	3767579	1			T50	1		T53	35		T55	1
valid_sources[0x10]	1395676	1			T51	1		T53	37		T54	1
valid_sources[0x11]	3379476	1			T51	4		T52	2		T53	35
valid_sources[0x12]	1400557	1			T50	3		T51	1		T53	35
valid_sources[0x13]	1401414	1			T53	24		T55	5		T67	4
valid_sources[0x14]	1557596	1			T50	1		T53	28		T55	5
valid_sources[0x15]	1401147	1			T50	1		T53	26		T54	2
valid_sources[0x16]	1545569	1			T50	2		T51	4		T53	26
valid_sources[0x17]	2291615	1			T1	1		T50	2		T53	34
valid_sources[0x18]	3283979	1			T53	25		T55	2		T63	1
valid_sources[0x19]	1406658	1			T53	27		T55	1		T65	1
valid_sources[0x1a]	1485806	1			T50	2		T51	2		T53	25
valid_sources[0x1b]	1400534	1			T50	2		T53	29		T65	2
valid_sources[0x1c]	1410576	1			T50	1		T51	3		T53	26
valid_sources[0x1d]	1432903	1			T50	2		T53	28		T55	3
valid_sources[0x1e]	1398362	1			T50	1		T51	2		T53	32
valid_sources[0x1f]	1392429	1			T50	5		T53	22		T55	3
valid_sources[0x20]	2024010	1			T2	1		T51	1		T53	23
valid_sources[0x21]	1403088	1			T2	1		T50	4		T53	33
valid_sources[0x22]	1399456	1			T50	7		T53	28		T55	3
valid_sources[0x23]	1398263	1			T50	5		T53	20		T54	1
valid_sources[0x24]	1495093	1			T2	1		T50	2		T51	2
valid_sources[0x25]	1405325	1			T1	1		T50	3		T53	32
valid_sources[0x26]	1409154	1			T51	3		T53	24		T55	12
valid_sources[0x27]	1481505	1			T50	2		T51	1		T53	30
valid_sources[0x28]	1389211	1			T50	3		T53	31		T54	1
valid_sources[0x29]	1400563	1			T50	1		T53	23		T54	2
valid_sources[0x2a]	1575936	1			T50	4		T53	29		T67	6
valid_sources[0x2b]	1512504	1			T50	3		T53	38		T55	7
valid_sources[0x2c]	3752318	1			T50	7		T53	23		T55	3
valid_sources[0x2d]	3351053	1			T50	3		T51	1		T53	35
valid_sources[0x2e]	1408889	1			T50	3		T51	3		T53	29
valid_sources[0x2f]	3743970	1			T50	2		T53	33		T54	1
valid_sources[0x30]	3865871	1			T50	5		T53	30		T54	1
valid_sources[0x31]	1901135	1			T50	3		T51	1		T52	1
valid_sources[0x32]	1537455	1			T2	1		T50	4		T51	2
valid_sources[0x33]	1399652	1			T2	2		T50	5		T51	10
valid_sources[0x34]	3726329	1			T50	2		T53	37		T54	1
valid_sources[0x35]	1389545	1			T50	1		T53	30		T54	2
valid_sources[0x36]	1397323	1			T50	2		T53	37		T67	4
valid_sources[0x37]	1402136	1			T50	1		T51	1		T53	30
valid_sources[0x38]	2232536	1			T50	2		T53	27		T55	4
valid_sources[0x39]	1394506	1			T50	1		T51	2		T53	30
valid_sources[0x3a]	1708685	1			T50	3		T51	3		T52	1
valid_sources[0x3b]	1439855	1			T1	1		T50	1		T53	33
valid_sources[0x3c]	4237509	1			T50	1		T53	32		T55	1
valid_sources[0x3d]	1390628	1			T50	3		T53	32		T55	4
valid_sources[0x3e]	2225471	1			T50	4		T52	10		T53	28
valid_sources[0x3f]	1403544	1			T1	1		T50	3		T51	2
valid_sources[0x40]	3825732	1			T1	1		T50	4		T53	21
valid_sources[0x41]	1404549	1			T53	35		T54	1		T55	7
valid_sources[0x42]	1402426	1			T50	4		T53	26		T55	7
valid_sources[0x43]	1395859	1			T1	1		T2	1		T50	4
valid_sources[0x44]	1399421	1			T51	13		T53	37		T67	1
valid_sources[0x45]	1396055	1			T50	2		T51	2		T53	27
valid_sources[0x46]	1396056	1			T53	34		T54	1		T67	10
valid_sources[0x47]	1400483	1			T51	3		T53	32		T56	1
valid_sources[0x48]	2052607	1			T1	1		T50	1		T51	1
valid_sources[0x49]	1390618	1			T50	4		T53	24		T55	1
valid_sources[0x4a]	2253772	1			T50	1		T53	28		T54	1
valid_sources[0x4b]	1396726	1			T50	1		T53	38		T55	1
valid_sources[0x4c]	4220088	1			T50	4		T53	25		T55	3
valid_sources[0x4d]	1484034	1			T50	2		T53	21		T55	2
valid_sources[0x4e]	2040573	1			T50	3		T51	4		T53	25
valid_sources[0x4f]	1395069	1			T53	24		T55	3		T67	2
valid_sources[0x50]	2117271	1			T50	3		T51	2		T53	29
valid_sources[0x51]	1400244	1			T50	2		T53	22		T54	1
valid_sources[0x52]	1504670	1			T50	2		T51	2		T53	25
valid_sources[0x53]	3410190	1			T50	2		T51	2		T53	23
valid_sources[0x54]	1397149	1			T1	1		T51	1		T53	32
valid_sources[0x55]	2045946	1			T50	5		T53	24		T55	2
valid_sources[0x56]	1396500	1			T2	2		T50	2		T52	3
valid_sources[0x57]	4260640	1			T50	1		T53	24		T55	4
valid_sources[0x58]	1925654	1			T50	2		T51	1		T53	25
valid_sources[0x59]	2267615	1			T50	4		T53	28		T55	9
valid_sources[0x5a]	1414874	1			T53	21		T55	2		T56	2
valid_sources[0x5b]	3588596	1			T50	1		T51	1		T53	29
valid_sources[0x5c]	1403231	1			T50	3		T51	1		T53	31
valid_sources[0x5d]	1404330	1			T50	1		T51	2		T52	1
valid_sources[0x5e]	1391396	1			T50	5		T51	1		T53	27
valid_sources[0x5f]	1435781	1			T50	4		T52	1		T53	26
valid_sources[0x60]	1400424	1			T1	1		T50	2		T53	30
valid_sources[0x61]	2055826	1			T51	4		T53	31		T54	3
valid_sources[0x62]	1401736	1			T1	1		T50	3		T51	7
valid_sources[0x63]	1507694	1			T50	2		T51	1		T53	34
valid_sources[0x64]	1398755	1			T50	3		T52	7		T53	22
valid_sources[0x65]	2304389	1			T50	2		T53	30		T55	6
valid_sources[0x66]	1399274	1			T50	1		T51	6		T53	34
valid_sources[0x67]	2042272	1			T50	2		T53	26		T55	10
valid_sources[0x68]	1389341	1			T50	6		T53	26		T54	1
valid_sources[0x69]	1403997	1			T2	1		T50	5		T51	1
valid_sources[0x6a]	1400133	1			T50	2		T51	7		T53	44
valid_sources[0x6b]	1940703	1			T50	1		T53	41		T55	8
valid_sources[0x6c]	1399698	1			T53	26		T55	1		T67	6
valid_sources[0x6d]	1402142	1			T3	1		T50	1		T53	35
valid_sources[0x6e]	1391574	1			T50	5		T53	32		T65	2
valid_sources[0x6f]	1409785	1			T51	1		T53	27		T55	4
valid_sources[0x70]	3199091	1			T50	1		T52	10		T53	31
valid_sources[0x71]	1396528	1			T50	6		T51	6		T53	23
valid_sources[0x72]	1408585	1			T50	1		T53	26		T54	1
valid_sources[0x73]	1403713	1			T50	1		T51	2		T53	36
valid_sources[0x74]	1555703	1			T1	1		T50	2		T51	1
valid_sources[0x75]	1396211	1			T50	1		T51	2		T53	25
valid_sources[0x76]	1405676	1			T50	2		T51	2		T53	23
valid_sources[0x77]	2246075	1			T50	1		T53	19		T54	1
valid_sources[0x78]	1396818	1			T50	1		T51	2		T53	31
valid_sources[0x79]	1401583	1			T50	2		T53	33		T55	1
valid_sources[0x7a]	1484472	1			T50	1		T51	1		T53	23
valid_sources[0x7b]	1852098	1			T50	2		T53	34		T54	1
valid_sources[0x7c]	1578585	1			T50	5		T51	7		T53	25
valid_sources[0x7d]	1406361	1			T50	1		T51	1		T53	18
valid_sources[0x7e]	1395451	1			T50	3		T53	30		T55	3
valid_sources[0x7f]	2296916	1			T50	3		T53	33		T55	2
valid_sources[0x80]	1399626	1			T2	1		T50	1		T53	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72552850

1

T1

3

T2

6

T3

1

values[0x0]

all_enables

biggest_size

61647845

1

T1

2

T2

3

T50

153

values[0x1]

all_enables

biggest_size

53152353

1

T1

3

T50

124

T51

24