Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

268629254

1

T1

14

T2

11

T51

323

full_word

187773677

1

T1

8

T2

9

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456402651	1			T1	22		T2	20		T3	1
auto[TlIntgErrCmd]	87	1			T113	5		T114	3		T117	4
auto[TlIntgErrData]	104	1			T113	2		T114	6		T117	4
auto[TlIntgErrBoth]	89	1			T113	3		T114	1		T117	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233694175

1

T1

11

T2

10

T3

1

auto[1]

222708756

1

T1

11

T2

10

T50

277

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161036504	1			T1	8		T2	4		T51	1
auto[TlIntgErrNone]	partial	auto[1]	107592493	1			T1	6		T2	7		T51	322
auto[TlIntgErrNone]	full_word	auto[0]	72657539	1			T1	3		T2	6		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	115116115	1			T1	5		T2	3		T50	277
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T113	2		T114	1		T117	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T113	2		T114	2		T117	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T113	1		T117	1		T119	2
auto[TlIntgErrData]	partial	auto[0]	56	1			T113	1		T114	3		T117	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T113	1		T114	3		T117	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T121	1		T147	1		T148	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T117	1		T149	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T117	1		T127	1		T119	4
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T113	2		T114	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T127	1		T150	1		T151	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T113	1		T152	1		T148	1