Module Definition
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Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 100.00 98.75 98.17 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00



Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 100.00 98.75 98.17 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00



Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 100.00 98.75 98.17 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00



Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 100.00 98.75 98.17 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00



Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.23 100.00 98.75 98.17 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00

Line Coverage for Module : prim_dom_and_2share
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1


Assert Coverage for Module : prim_dom_and_2share
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 777270785 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 777270785 0 0
T4 3543240 1310880 0 0
T5 766695 330720 0 0
T6 611725 42240 0 0
T10 739850 333840 0 0
T15 12645 200 0 0
T16 6490 0 0 0
T17 1195720 66240 0 0
T18 588870 320640 0 0
T19 2549845 83520 0 0
T20 731480 1921920 0 0
T21 0 7440 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1


Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155454157 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155454157 0 0
T4 708648 262176 0 0
T5 153339 66144 0 0
T6 122345 8448 0 0
T10 147970 66768 0 0
T15 2529 40 0 0
T16 1298 0 0 0
T17 239144 13248 0 0
T18 117774 64128 0 0
T19 509969 16704 0 0
T20 146296 384384 0 0
T21 0 1488 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1


Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155454157 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155454157 0 0
T4 708648 262176 0 0
T5 153339 66144 0 0
T6 122345 8448 0 0
T10 147970 66768 0 0
T15 2529 40 0 0
T16 1298 0 0 0
T17 239144 13248 0 0
T18 117774 64128 0 0
T19 509969 16704 0 0
T20 146296 384384 0 0
T21 0 1488 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1


Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155454157 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155454157 0 0
T4 708648 262176 0 0
T5 153339 66144 0 0
T6 122345 8448 0 0
T10 147970 66768 0 0
T15 2529 40 0 0
T16 1298 0 0 0
T17 239144 13248 0 0
T18 117774 64128 0 0
T19 509969 16704 0 0
T20 146296 384384 0 0
T21 0 1488 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1


Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155454157 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155454157 0 0
T4 708648 262176 0 0
T5 153339 66144 0 0
T6 122345 8448 0 0
T10 147970 66768 0 0
T15 2529 40 0 0
T16 1298 0 0 0
T17 239144 13248 0 0
T18 117774 64128 0 0
T19 509969 16704 0 0
T20 146296 384384 0 0
T21 0 1488 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1


Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155454157 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155454157 0 0
T4 708648 262176 0 0
T5 153339 66144 0 0
T6 122345 8448 0 0
T10 147970 66768 0 0
T15 2529 40 0 0
T16 1298 0 0 0
T17 239144 13248 0 0
T18 117774 64128 0 0
T19 509969 16704 0 0
T20 146296 384384 0 0
T21 0 1488 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%