Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	115078237	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1255	1255	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115078237	0	0
T4	0	159955	0	0
T5	0	46502	0	0
T51	1455	725	0	0
T52	2164	0	0	0
T53	15710	0	0	0
T54	1862	9	0	0
T55	5641	0	0	0
T56	1118	0	0	0
T57	2018	54	0	0
T58	0	407	0	0
T59	0	154	0	0
T60	0	526	0	0
T61	0	447	0	0
T62	0	739	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1255	1255	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	201919578	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1255	1255	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	201919578	0	0
T4	0	720134	0	0
T5	0	46502	0	0
T51	1455	363	0	0
T52	2164	0	0	0
T53	15710	0	0	0
T54	1862	33	0	0
T55	5641	0	0	0
T56	1118	0	0	0
T57	2018	105	0	0
T58	0	1027	0	0
T59	0	147	0	0
T60	0	402	0	0
T61	0	350	0	0
T62	0	449	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1255	1255	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	324257139	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1255	1255	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	324257139	0	0
T1	731	22	0	0
T2	1422	20	0	0
T3	1213	1	0	0
T50	4417	600	0	0
T51	1455	3	0	0
T52	2164	137	0	0
T53	15710	7399	0	0
T54	1862	120	0	0
T55	5641	820	0	0
T56	1118	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1255	1255	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	578572710	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1255	1255	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	578572710	0	0
T1	731	22	0	0
T2	1422	94	0	0
T3	1213	1	0	0
T50	4417	553	0	0
T51	1455	3	0	0
T52	2164	254	0	0
T53	15710	7343	0	0
T54	1862	181	0	0
T55	5641	748	0	0
T56	1118	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	731	668	0	0
T2	1422	1322	0	0
T3	1213	1123	0	0
T50	4417	4362	0	0
T51	1455	1386	0	0
T52	2164	2037	0	0
T53	15710	15619	0	0
T54	1862	1728	0	0
T55	5641	5366	0	0
T56	1118	1023	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1255	1255	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0