Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1531132	0	0
entropy_period_rd_A	2147483647	3017	0	0
intr_enable_rd_A	2147483647	3649	0	0
prefix_0_rd_A	2147483647	3140	0	0
prefix_10_rd_A	2147483647	3246	0	0
prefix_1_rd_A	2147483647	3388	0	0
prefix_2_rd_A	2147483647	3272	0	0
prefix_3_rd_A	2147483647	3220	0	0
prefix_4_rd_A	2147483647	3301	0	0
prefix_5_rd_A	2147483647	3436	0	0
prefix_6_rd_A	2147483647	3196	0	0
prefix_7_rd_A	2147483647	3576	0	0
prefix_8_rd_A	2147483647	3232	0	0
prefix_9_rd_A	2147483647	3335	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1531132	0	0
T54	1862	1	0	0
T55	5641	0	0	0
T56	1118	0	0	0
T57	2018	0	0	0
T58	0	206	0	0
T59	0	185	0	0
T60	0	272	0	0
T61	0	243	0	0
T62	0	22	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	0	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T117	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T127	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3017	0	0
T43	0	79	0	0
T57	2018	2	0	0
T58	7582	0	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	10	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	2807	0	0	0
T70	1346	0	0	0
T72	0	190	0	0
T114	0	68	0	0
T115	0	50	0	0
T117	0	37	0	0
T122	0	16	0	0
T138	0	41	0	0
T139	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3649	0	0
T2	1422	9	0	0
T3	1213	0	0	0
T50	4417	0	0	0
T51	1455	0	0	0
T52	2164	0	0	0
T53	15710	0	0	0
T54	1862	0	0	0
T55	5641	0	0	0
T56	1118	0	0	0
T57	2018	0	0	0
T64	0	15	0	0
T65	0	10	0	0
T69	0	2	0	0
T114	0	80	0	0
T115	0	65	0	0
T117	0	87	0	0
T122	0	31	0	0
T140	0	5	0	0
T141	0	5	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3140	0	0
T57	2018	3	0	0
T58	7582	0	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	8	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	2807	4	0	0
T70	1346	0	0	0
T72	0	152	0	0
T114	0	33	0	0
T115	0	45	0	0
T117	0	54	0	0
T122	0	7	0	0
T138	0	19	0	0
T139	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3246	0	0
T42	0	137	0	0
T43	0	78	0	0
T58	7582	0	0	0
T65	3448	11	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	2807	0	0	0
T70	1346	0	0	0
T72	0	142	0	0
T113	4587	0	0	0
T114	0	41	0	0
T115	11235	50	0	0
T117	0	52	0	0
T122	3088	9	0	0
T138	0	27	0	0
T142	0	32	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3388	0	0
T54	1862	1	0	0
T55	5641	0	0	0
T56	1118	0	0	0
T57	2018	3	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	2	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	0	10	0	0
T114	0	34	0	0
T115	0	39	0	0
T117	0	36	0	0
T122	0	4	0	0
T138	0	31	0	0
T139	0	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3272	0	0
T52	2164	4	0	0
T53	15710	0	0	0
T54	1862	0	0	0
T55	5641	0	0	0
T56	1118	0	0	0
T57	2018	5	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	3	0	0
T66	1618	0	0	0
T69	0	10	0	0
T114	0	55	0	0
T115	0	48	0	0
T117	0	47	0	0
T122	0	6	0	0
T138	0	13	0	0
T139	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3220	0	0
T54	1862	2	0	0
T55	5641	0	0	0
T56	1118	0	0	0
T57	2018	0	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	10	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	0	3	0	0
T72	0	152	0	0
T114	0	51	0	0
T115	0	40	0	0
T117	0	57	0	0
T122	0	4	0	0
T138	0	23	0	0
T139	0	2	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3301	0	0
T42	0	76	0	0
T43	0	101	0	0
T58	7582	0	0	0
T65	3448	6	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	2807	2	0	0
T70	1346	0	0	0
T72	0	169	0	0
T113	4587	0	0	0
T114	0	24	0	0
T115	11235	26	0	0
T117	0	36	0	0
T122	3088	18	0	0
T138	0	30	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3436	0	0
T42	0	145	0	0
T43	0	55	0	0
T57	2018	4	0	0
T58	7582	0	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	22	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	2807	0	0	0
T70	1346	0	0	0
T72	0	134	0	0
T114	0	43	0	0
T115	0	46	0	0
T117	0	56	0	0
T122	0	9	0	0
T138	0	32	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3196	0	0
T42	0	100	0	0
T43	0	93	0	0
T58	7582	0	0	0
T59	2723	0	0	0
T69	2807	6	0	0
T70	1346	0	0	0
T72	0	155	0	0
T113	4587	0	0	0
T114	13363	43	0	0
T115	11235	47	0	0
T117	0	44	0	0
T122	3088	7	0	0
T123	1439	0	0	0
T124	1306	0	0	0
T138	0	16	0	0
T139	0	8	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3576	0	0
T43	0	93	0	0
T58	7582	0	0	0
T65	3448	16	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	2807	9	0	0
T70	1346	0	0	0
T72	0	137	0	0
T113	4587	0	0	0
T114	0	36	0	0
T115	11235	34	0	0
T117	0	36	0	0
T122	3088	9	0	0
T138	0	20	0	0
T139	0	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3232	0	0
T43	0	80	0	0
T58	7582	0	0	0
T65	3448	12	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	2807	3	0	0
T70	1346	0	0	0
T72	0	95	0	0
T113	4587	0	0	0
T114	0	25	0	0
T115	11235	35	0	0
T117	0	39	0	0
T122	3088	9	0	0
T138	0	24	0	0
T139	0	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3335	0	0
T54	1862	4	0	0
T55	5641	0	0	0
T56	1118	0	0	0
T57	2018	0	0	0
T63	924	0	0	0
T64	839	0	0	0
T65	3448	8	0	0
T66	1618	0	0	0
T67	9133	0	0	0
T68	1504	0	0	0
T69	0	2	0	0
T72	0	127	0	0
T114	0	44	0	0
T115	0	69	0	0
T117	0	23	0	0
T122	0	11	0	0
T138	0	31	0	0
T139	0	7	0	0