Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	265682241	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

191671889

1

T1

88

T2

123

T3

52

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	236572869	1			T1	58		T2	121		T3	63
values[0x0]	105918847	1			T1	30		T2	87		T3	82
values[0x1]	114862414	1			T1	30		T2	148		T3	160

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	206223118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

251131012

1

T1

99

T2

200

T3

151

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1866824	1			T71	6		T72	1		T113	2
valid_sources[0x01]	1410706	1			T1	3		T3	12		T69	2
valid_sources[0x02]	1413790	1			T3	14		T69	2		T70	33
valid_sources[0x03]	1431666	1			T1	21		T69	7		T72	1
valid_sources[0x04]	1416361	1			T3	6		T69	2		T70	14
valid_sources[0x05]	1406136	1			T2	47		T69	3		T73	1
valid_sources[0x06]	1834545	1			T69	4		T71	3		T72	1
valid_sources[0x07]	1412476	1			T3	2		T71	2		T112	14
valid_sources[0x08]	1409491	1			T72	3		T112	21		T74	3
valid_sources[0x09]	1414467	1			T3	3		T71	1		T73	1
valid_sources[0x0a]	2309646	1			T71	3		T73	1		T72	1
valid_sources[0x0b]	1417403	1			T71	1		T72	5		T112	26
valid_sources[0x0c]	1863010	1			T71	8		T112	12		T74	1
valid_sources[0x0d]	1420350	1			T70	17		T73	1		T112	3
valid_sources[0x0e]	1433418	1			T66	1		T112	13		T127	13
valid_sources[0x0f]	1401864	1			T66	1		T70	10		T71	1
valid_sources[0x10]	1410934	1			T3	3		T71	4		T72	1
valid_sources[0x11]	1808061	1			T73	2		T112	2		T127	10
valid_sources[0x12]	2270185	1			T70	8		T71	9		T73	1
valid_sources[0x13]	1536682	1			T3	2		T68	2		T69	2
valid_sources[0x14]	1549984	1			T69	5		T70	9		T71	7
valid_sources[0x15]	1411218	1			T3	2		T66	1		T69	3
valid_sources[0x16]	1416937	1			T66	1		T68	11		T69	2
valid_sources[0x17]	3353383	1			T69	8		T71	6		T73	1
valid_sources[0x18]	1409894	1			T69	2		T70	2		T71	3
valid_sources[0x19]	1442385	1			T69	1		T70	20		T71	2
valid_sources[0x1a]	1408971	1			T68	4		T112	9		T74	1
valid_sources[0x1b]	1410506	1			T69	8		T70	21		T71	4
valid_sources[0x1c]	1417772	1			T68	3		T69	2		T70	14
valid_sources[0x1d]	1412310	1			T3	2		T69	1		T70	38
valid_sources[0x1e]	2045707	1			T69	3		T73	2		T112	15
valid_sources[0x1f]	2996758	1			T69	6		T70	8		T112	2
valid_sources[0x20]	1414248	1			T66	1		T69	2		T70	8
valid_sources[0x21]	2328771	1			T3	10		T69	2		T70	2
valid_sources[0x22]	3736683	1			T71	5		T112	7		T74	1
valid_sources[0x23]	1415748	1			T73	1		T131	5		T112	13
valid_sources[0x24]	1534733	1			T70	5		T71	6		T73	1
valid_sources[0x25]	3756441	1			T69	2		T73	1		T72	2
valid_sources[0x26]	1416217	1			T71	2		T73	1		T72	1
valid_sources[0x27]	1418111	1			T69	2		T112	10		T74	2
valid_sources[0x28]	1669270	1			T3	16		T70	16		T71	2
valid_sources[0x29]	1424813	1			T3	3		T70	15		T71	4
valid_sources[0x2a]	1415151	1			T3	3		T71	5		T72	1
valid_sources[0x2b]	3758410	1			T3	2		T69	3		T71	2
valid_sources[0x2c]	1438068	1			T3	7		T70	18		T71	2
valid_sources[0x2d]	1417431	1			T112	11		T127	18		T134	1
valid_sources[0x2e]	1422924	1			T3	5		T112	8		T127	30
valid_sources[0x2f]	1417093	1			T68	1		T71	2		T73	2
valid_sources[0x30]	1418044	1			T71	1		T112	20		T74	2
valid_sources[0x31]	1559683	1			T3	3		T70	10		T71	2
valid_sources[0x32]	1479211	1			T68	7		T71	1		T112	20
valid_sources[0x33]	1413128	1			T69	1		T70	9		T71	2
valid_sources[0x34]	1427868	1			T112	11		T74	1		T127	6
valid_sources[0x35]	5233225	1			T68	3		T71	1		T112	19
valid_sources[0x36]	1414370	1			T69	3		T70	8		T71	1
valid_sources[0x37]	1418401	1			T69	1		T112	12		T74	2
valid_sources[0x38]	1421067	1			T68	3		T69	2		T71	8
valid_sources[0x39]	1413468	1			T3	4		T71	5		T73	3
valid_sources[0x3a]	1499520	1			T3	14		T69	2		T70	8
valid_sources[0x3b]	1417664	1			T1	10		T2	108		T70	15
valid_sources[0x3c]	1865203	1			T3	4		T69	1		T112	13
valid_sources[0x3d]	2600541	1			T71	9		T73	2		T112	10
valid_sources[0x3e]	1420045	1			T73	1		T112	11		T74	2
valid_sources[0x3f]	1548936	1			T1	44		T68	1		T70	10
valid_sources[0x40]	2266424	1			T69	4		T71	3		T73	2
valid_sources[0x41]	1554768	1			T66	1		T72	1		T112	13
valid_sources[0x42]	1409276	1			T69	2		T70	20		T71	2
valid_sources[0x43]	1410707	1			T68	1		T69	2		T70	8
valid_sources[0x44]	1419405	1			T69	1		T70	12		T71	2
valid_sources[0x45]	2941628	1			T69	5		T71	4		T72	3
valid_sources[0x46]	1420537	1			T68	14		T69	6		T112	3
valid_sources[0x47]	3588845	1			T3	1		T69	1		T73	2
valid_sources[0x48]	1419730	1			T70	13		T71	2		T112	16
valid_sources[0x49]	2915929	1			T71	2		T73	4		T72	2
valid_sources[0x4a]	1416829	1			T69	1		T73	3		T112	15
valid_sources[0x4b]	1424590	1			T71	2		T73	2		T112	27
valid_sources[0x4c]	1413251	1			T69	1		T71	9		T73	1
valid_sources[0x4d]	1412566	1			T3	7		T71	6		T112	3
valid_sources[0x4e]	1415857	1			T112	4		T127	10		T133	3
valid_sources[0x4f]	2351412	1			T66	2		T69	3		T71	2
valid_sources[0x50]	1413177	1			T1	5		T68	1		T69	2
valid_sources[0x51]	1534146	1			T70	13		T71	4		T73	1
valid_sources[0x52]	1427593	1			T2	42		T68	1		T71	7
valid_sources[0x53]	1517191	1			T3	4		T69	1		T73	2
valid_sources[0x54]	1403828	1			T71	2		T112	19		T74	2
valid_sources[0x55]	2450736	1			T69	6		T70	6		T71	8
valid_sources[0x56]	3501562	1			T71	3		T73	4		T112	4
valid_sources[0x57]	1411601	1			T70	6		T112	4		T74	1
valid_sources[0x58]	1413354	1			T3	1		T71	3		T112	6
valid_sources[0x59]	2380672	1			T69	3		T71	3		T73	5
valid_sources[0x5a]	2333427	1			T66	1		T69	1		T72	1
valid_sources[0x5b]	4328725	1			T66	1		T69	1		T73	2
valid_sources[0x5c]	1879295	1			T70	7		T71	2		T112	3
valid_sources[0x5d]	1458599	1			T73	1		T72	2		T112	5
valid_sources[0x5e]	2174427	1			T69	1		T71	1		T112	17
valid_sources[0x5f]	1428376	1			T3	5		T68	3		T69	27
valid_sources[0x60]	1522291	1			T73	3		T112	10		T74	1
valid_sources[0x61]	1412476	1			T71	3		T73	1		T72	2
valid_sources[0x62]	1414831	1			T3	2		T73	4		T74	1
valid_sources[0x63]	1410818	1			T69	6		T73	2		T112	9
valid_sources[0x64]	1414565	1			T70	8		T71	2		T72	1
valid_sources[0x65]	1572107	1			T72	1		T112	2		T127	8
valid_sources[0x66]	1416963	1			T2	58		T69	1		T71	7
valid_sources[0x67]	2061081	1			T2	70		T69	4		T70	14
valid_sources[0x68]	1438195	1			T69	13		T71	2		T73	1
valid_sources[0x69]	1415180	1			T70	11		T71	6		T73	2
valid_sources[0x6a]	1420548	1			T70	7		T112	5		T74	3
valid_sources[0x6b]	2830897	1			T69	1		T112	11		T94	4
valid_sources[0x6c]	1407916	1			T69	7		T70	18		T71	2
valid_sources[0x6d]	1408966	1			T69	1		T71	2		T73	5
valid_sources[0x6e]	1426949	1			T3	2		T73	1		T112	3
valid_sources[0x6f]	1416352	1			T68	7		T73	1		T112	6
valid_sources[0x70]	1416498	1			T3	8		T69	2		T71	3
valid_sources[0x71]	1416939	1			T69	8		T71	3		T112	2
valid_sources[0x72]	1427143	1			T3	4		T67	1		T68	5
valid_sources[0x73]	1428530	1			T68	1		T69	1		T71	5
valid_sources[0x74]	1409107	1			T68	6		T69	1		T71	3
valid_sources[0x75]	1415841	1			T3	10		T73	1		T72	2
valid_sources[0x76]	3768385	1			T1	5		T73	1		T112	22
valid_sources[0x77]	3356008	1			T70	3		T71	2		T73	2
valid_sources[0x78]	1407606	1			T3	5		T69	4		T70	11
valid_sources[0x79]	1855166	1			T3	2		T69	1		T70	18
valid_sources[0x7a]	1432681	1			T68	5		T72	2		T112	4
valid_sources[0x7b]	1415157	1			T3	2		T69	4		T70	6
valid_sources[0x7c]	1407273	1			T70	5		T71	2		T112	8
valid_sources[0x7d]	1747544	1			T3	2		T69	1		T71	6
valid_sources[0x7e]	1421617	1			T69	1		T72	3		T112	15
valid_sources[0x7f]	1421752	1			T69	2		T70	41		T71	2
valid_sources[0x80]	1403835	1			T3	10		T68	3		T70	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74382586

1

T1

33

T2

54

T3

27

values[0x0]

all_enables

biggest_size

62962953

1

T1

27

T2

36

T3

14

values[0x1]

all_enables

biggest_size

54326350

1

T1

28

T2

33

T3

11