Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

273889766

1

T1

30

T2

233

T3

273

full_word

192182321

1

T1

88

T2

123

T3

52

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	466071767	1			T1	118		T2	356		T3	325
auto[TlIntgErrCmd]	107	1			T112	8		T127	8		T128	1
auto[TlIntgErrData]	116	1			T112	7		T127	4		T128	12
auto[TlIntgErrBoth]	97	1			T112	5		T127	8		T128	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238143412

1

T1

58

T2

121

T3

67

auto[1]

227928675

1

T1

60

T2

235

T3

258

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	163632667	1			T1	25		T2	67		T3	40
auto[TlIntgErrNone]	partial	auto[1]	110256806	1			T1	5		T2	166		T3	233
auto[TlIntgErrNone]	full_word	auto[0]	74510588	1			T1	33		T2	54		T3	27
auto[TlIntgErrNone]	full_word	auto[1]	117671706	1			T1	55		T2	69		T3	25
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T112	4		T127	4		T128	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T112	3		T127	3		T129	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T112	1		T127	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T130	1		T160	2		T161	1
auto[TlIntgErrData]	partial	auto[0]	59	1			T112	5		T127	3		T128	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T112	1		T127	1		T128	6
auto[TlIntgErrData]	full_word	auto[0]	7	1			T112	1		T129	1		T160	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T128	1		T160	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T112	2		T127	2		T128	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T112	3		T127	5		T128	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T127	1		T160	1		T163	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T164	1		T160	1		-	-