Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	349973	0	0
RunThenComplete_M	2147483647	3140178	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	349973	0	0
T5	23129	9	0	0
T6	1356	0	0	0
T10	369015	246	0	0
T11	1648	0	0	0
T12	116415	22	0	0
T13	83016	21	0	0
T14	0	63	0	0
T15	177358	2337	0	0
T16	2519	0	0	0
T35	695115	310	0	0
T36	334477	246	0	0
T37	0	85	0	0
T44	0	9	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3140178	0	0
T5	23129	31	0	0
T6	1356	0	0	0
T10	369015	5427	0	0
T11	1648	0	0	0
T12	116415	728	0	0
T13	83016	96	0	0
T14	0	2085	0	0
T15	177358	13147	0	0
T16	2519	0	0	0
T35	695115	5462	0	0
T36	334477	5427	0	0
T37	0	444	0	0
T44	0	31	0	0