Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	117375385	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1264	1264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117375385	0	0
T2	3283	192	0	0
T3	1639	466	0	0
T65	1082	0	0	0
T66	2470	0	0	0
T67	1314	0	0	0
T68	2650	0	0	0
T69	10201	259	0	0
T70	3667	0	0	0
T71	1989	0	0	0
T72	0	143	0	0
T73	2784	544	0	0
T74	0	292	0	0
T75	0	262	0	0
T76	0	221	0	0
T77	0	722	0	0
T80	0	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1264	1264	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	205460292	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1264	1264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	205460292	0	0
T2	3283	180	0	0
T3	1639	238	0	0
T65	1082	0	0	0
T66	2470	0	0	0
T67	1314	0	0	0
T68	2650	0	0	0
T69	10201	258	0	0
T70	3667	0	0	0
T71	1989	0	0	0
T72	0	142	0	0
T73	2784	1104	0	0
T74	0	278	0	0
T75	0	206	0	0
T76	0	210	0	0
T77	0	2120	0	0
T80	0	554	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1264	1264	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	330491974	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1264	1264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	330491974	0	0
T1	1306	232	0	0
T2	3283	186	0	0
T3	1639	146	0	0
T65	1082	38	0	0
T66	2470	22	0	0
T67	1314	1	0	0
T68	2650	170	0	0
T69	10201	1089	0	0
T70	3667	2427	0	0
T71	1989	1307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1264	1264	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	591062535	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1264	1264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	591062535	0	0
T1	1306	118	0	0
T2	3283	176	0	0
T3	1639	80	0	0
T65	1082	38	0	0
T66	2470	22	0	0
T67	1314	1	0	0
T68	2650	158	0	0
T69	10201	1042	0	0
T70	3667	1274	0	0
T71	1989	684	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1306	1210	0	0
T2	3283	3214	0	0
T3	1639	1579	0	0
T65	1082	1011	0	0
T66	2470	2415	0	0
T67	1314	1232	0	0
T68	2650	2422	0	0
T69	10201	10120	0	0
T70	3667	3613	0	0
T71	1989	1937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1264	1264	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0