Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1846540	0	0
entropy_period_rd_A	2147483647	2120	0	0
intr_enable_rd_A	2147483647	2804	0	0
prefix_0_rd_A	2147483647	1814	0	0
prefix_10_rd_A	2147483647	1910	0	0
prefix_1_rd_A	2147483647	2035	0	0
prefix_2_rd_A	2147483647	2006	0	0
prefix_3_rd_A	2147483647	2030	0	0
prefix_4_rd_A	2147483647	1927	0	0
prefix_5_rd_A	2147483647	2065	0	0
prefix_6_rd_A	2147483647	1839	0	0
prefix_7_rd_A	2147483647	1985	0	0
prefix_8_rd_A	2147483647	1976	0	0
prefix_9_rd_A	2147483647	1990	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1846540	0	0
T2	3283	1	0	0
T3	1639	1	0	0
T65	1082	0	0	0
T66	2470	0	0	0
T67	1314	0	0	0
T68	2650	0	0	0
T69	10201	258	0	0
T70	3667	0	0	0
T71	1989	0	0	0
T72	0	96	0	0
T73	2784	0	0	0
T74	0	185	0	0
T75	0	105	0	0
T76	0	69	0	0
T112	0	2	0	0
T127	0	5	0	0
T129	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2120	0	0
T75	2281	0	0	0
T80	0	12	0	0
T95	11545	63	0	0
T96	11171	21	0	0
T97	0	37	0	0
T105	2638	0	0	0
T127	24047	152	0	0
T128	25410	110	0	0
T129	0	129	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	12	0	0
T137	0	99	0	0
T143	0	43	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2804	0	0
T75	2281	0	0	0
T80	0	3	0	0
T95	11545	119	0	0
T96	11171	42	0	0
T97	0	64	0	0
T105	2638	0	0	0
T127	24047	180	0	0
T128	25410	125	0	0
T129	0	141	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	12	0	0
T137	0	104	0	0
T143	0	25	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1814	0	0
T75	2281	0	0	0
T80	0	5	0	0
T95	11545	42	0	0
T96	11171	15	0	0
T97	0	56	0	0
T105	2638	0	0	0
T127	24047	100	0	0
T128	25410	65	0	0
T129	0	59	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	5	0	0
T137	0	113	0	0
T143	0	40	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1910	0	0
T75	2281	0	0	0
T80	0	15	0	0
T95	11545	32	0	0
T96	11171	15	0	0
T97	0	53	0	0
T105	2638	0	0	0
T127	24047	78	0	0
T128	25410	66	0	0
T129	0	85	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	0	0	0
T137	0	96	0	0
T139	0	436	0	0
T143	0	23	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2035	0	0
T75	2281	0	0	0
T80	0	9	0	0
T95	11545	31	0	0
T96	11171	26	0	0
T97	0	28	0	0
T105	2638	0	0	0
T127	24047	63	0	0
T128	25410	101	0	0
T129	0	61	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	47	0	0
T137	0	122	0	0
T143	0	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2006	0	0
T75	2281	0	0	0
T80	0	10	0	0
T95	11545	47	0	0
T96	11171	51	0	0
T97	0	28	0	0
T105	2638	0	0	0
T127	24047	98	0	0
T128	25410	70	0	0
T129	0	79	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	22	0	0
T137	0	132	0	0
T143	0	23	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2030	0	0
T75	2281	0	0	0
T80	0	13	0	0
T95	11545	50	0	0
T96	11171	26	0	0
T97	0	28	0	0
T105	2638	0	0	0
T127	24047	80	0	0
T128	25410	66	0	0
T129	0	86	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	12	0	0
T137	0	153	0	0
T143	0	6	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1927	0	0
T75	2281	0	0	0
T80	0	4	0	0
T95	11545	51	0	0
T96	11171	31	0	0
T97	0	28	0	0
T105	2638	0	0	0
T127	24047	77	0	0
T128	25410	61	0	0
T129	0	67	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	26	0	0
T137	0	115	0	0
T143	0	13	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2065	0	0
T75	2281	0	0	0
T80	0	7	0	0
T95	11545	41	0	0
T96	11171	23	0	0
T97	0	51	0	0
T105	2638	0	0	0
T127	24047	89	0	0
T128	25410	64	0	0
T129	0	74	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	37	0	0
T137	0	116	0	0
T143	0	29	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1839	0	0
T75	2281	0	0	0
T80	0	9	0	0
T95	11545	26	0	0
T96	11171	13	0	0
T97	0	24	0	0
T105	2638	0	0	0
T127	24047	85	0	0
T128	25410	62	0	0
T129	0	79	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	20	0	0
T137	0	112	0	0
T143	0	36	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1985	0	0
T75	2281	0	0	0
T80	0	5	0	0
T95	11545	31	0	0
T96	11171	31	0	0
T97	0	24	0	0
T105	2638	0	0	0
T127	24047	90	0	0
T128	25410	57	0	0
T129	0	105	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	48	0	0
T137	0	103	0	0
T143	0	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1976	0	0
T75	2281	0	0	0
T80	0	7	0	0
T95	11545	48	0	0
T96	11171	35	0	0
T97	0	49	0	0
T105	2638	0	0	0
T127	24047	93	0	0
T128	25410	84	0	0
T129	0	66	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	1	0	0
T137	0	108	0	0
T143	0	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1990	0	0
T75	2281	0	0	0
T80	0	9	0	0
T95	11545	64	0	0
T96	11171	16	0	0
T97	0	21	0	0
T105	2638	0	0	0
T127	24047	74	0	0
T128	25410	69	0	0
T129	0	101	0	0
T132	2084	0	0	0
T133	2562	0	0	0
T134	2654	0	0	0
T135	6297	15	0	0
T137	0	92	0	0
T143	0	27	0	0