Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	263450974	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

189679245

1

T1

1851

T2

178

T3

3567

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	234544390	1			T1	1526		T2	121		T3	6845
values[0x0]	104881255	1			T1	618		T2	69		T3	52
values[0x1]	113704574	1			T1	592		T2	53		T3	68

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	204473400	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

248656819

1

T1

2106

T2

194

T3

4228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2133264	1			T1	18		T3	22		T60	3
valid_sources[0x01]	1408929	1			T1	6		T3	24		T60	13
valid_sources[0x02]	1412517	1			T1	17		T3	18		T60	2
valid_sources[0x03]	1419889	1			T1	15		T3	29		T60	10
valid_sources[0x04]	1415528	1			T1	12		T3	40		T60	2
valid_sources[0x05]	2071048	1			T1	6		T3	55		T60	4
valid_sources[0x06]	1410876	1			T1	16		T3	3		T60	9
valid_sources[0x07]	1500244	1			T1	7		T3	30		T60	4
valid_sources[0x08]	1411233	1			T1	11		T3	41		T60	3
valid_sources[0x09]	1417848	1			T1	9		T3	34		T60	9
valid_sources[0x0a]	1405179	1			T1	14		T3	13		T60	3
valid_sources[0x0b]	1427994	1			T1	8		T3	50		T60	8
valid_sources[0x0c]	1603516	1			T1	15		T3	23		T60	5
valid_sources[0x0d]	1643902	1			T1	7		T3	16		T60	9
valid_sources[0x0e]	1633184	1			T1	5		T3	30		T60	9
valid_sources[0x0f]	1416842	1			T1	17		T3	17		T60	6
valid_sources[0x10]	1517594	1			T1	14		T3	14		T60	3
valid_sources[0x11]	2299528	1			T1	11		T3	8		T60	3
valid_sources[0x12]	1419066	1			T1	7		T3	21		T60	6
valid_sources[0x13]	1431743	1			T1	7		T3	13		T60	4
valid_sources[0x14]	1498894	1			T1	13		T3	25		T60	7
valid_sources[0x15]	1439432	1			T1	7		T3	17		T60	5
valid_sources[0x16]	1415180	1			T1	6		T3	35		T60	3
valid_sources[0x17]	1590016	1			T1	17		T3	7		T60	5
valid_sources[0x18]	1466688	1			T1	7		T3	28		T60	7
valid_sources[0x19]	1446046	1			T1	13		T3	54		T60	5
valid_sources[0x1a]	1413056	1			T1	14		T3	21		T60	4
valid_sources[0x1b]	1415170	1			T1	6		T3	35		T60	7
valid_sources[0x1c]	1411165	1			T1	18		T3	24		T60	2
valid_sources[0x1d]	1413118	1			T1	13		T3	26		T60	8
valid_sources[0x1e]	1403637	1			T1	7		T3	21		T60	2
valid_sources[0x1f]	1406900	1			T1	8		T3	45		T60	6
valid_sources[0x20]	3770651	1			T1	8		T3	47		T60	9
valid_sources[0x21]	1412632	1			T1	5		T3	18		T60	1
valid_sources[0x22]	1450250	1			T1	11		T3	42		T60	4
valid_sources[0x23]	1413368	1			T1	12		T3	25		T60	1
valid_sources[0x24]	1413470	1			T1	9		T60	6		T64	1
valid_sources[0x25]	1872224	1			T1	7		T3	23		T60	3
valid_sources[0x26]	1415657	1			T1	6		T3	84		T60	15
valid_sources[0x27]	2254350	1			T1	14		T3	29		T60	7
valid_sources[0x28]	1614904	1			T1	9		T3	21		T60	11
valid_sources[0x29]	1540455	1			T1	15		T3	28		T60	14
valid_sources[0x2a]	1418145	1			T1	12		T3	51		T60	6
valid_sources[0x2b]	1420403	1			T1	12		T3	12		T60	5
valid_sources[0x2c]	1412865	1			T1	3		T3	26		T60	2
valid_sources[0x2d]	1412216	1			T1	5		T3	30		T60	1
valid_sources[0x2e]	1415175	1			T1	10		T3	48		T60	5
valid_sources[0x2f]	2179330	1			T1	14		T3	15		T60	5
valid_sources[0x30]	2307444	1			T1	11		T3	6		T60	3
valid_sources[0x31]	1429835	1			T1	8		T3	11		T60	2
valid_sources[0x32]	2073309	1			T1	7		T3	4		T60	2
valid_sources[0x33]	1588328	1			T1	11		T3	19		T60	3
valid_sources[0x34]	1448702	1			T1	12		T3	52		T60	7
valid_sources[0x35]	1403968	1			T1	8		T3	10		T60	4
valid_sources[0x36]	1413886	1			T1	4		T3	32		T60	4
valid_sources[0x37]	1587243	1			T1	13		T3	13		T60	2
valid_sources[0x38]	2277069	1			T1	6		T3	25		T60	11
valid_sources[0x39]	4250225	1			T1	15		T3	36		T60	6
valid_sources[0x3a]	2502702	1			T1	9		T3	55		T60	9
valid_sources[0x3b]	1424644	1			T1	12		T3	8		T60	2
valid_sources[0x3c]	1415719	1			T1	8		T3	14		T60	12
valid_sources[0x3d]	1422424	1			T1	9		T3	24		T60	6
valid_sources[0x3e]	1405420	1			T1	5		T3	20		T60	5
valid_sources[0x3f]	1407858	1			T1	13		T3	29		T60	9
valid_sources[0x40]	3513051	1			T1	11		T3	27		T60	9
valid_sources[0x41]	1410982	1			T1	10		T2	31		T3	42
valid_sources[0x42]	1409434	1			T1	11		T3	28		T60	1
valid_sources[0x43]	1590221	1			T1	13		T3	54		T60	6
valid_sources[0x44]	1729631	1			T1	9		T3	47		T60	4
valid_sources[0x45]	1404515	1			T1	9		T3	9		T60	4
valid_sources[0x46]	1407610	1			T1	5		T3	50		T60	5
valid_sources[0x47]	1413910	1			T1	13		T3	32		T60	13
valid_sources[0x48]	1414091	1			T1	13		T3	32		T60	3
valid_sources[0x49]	2314908	1			T1	10		T3	13		T60	8
valid_sources[0x4a]	1410624	1			T1	15		T3	16		T60	4
valid_sources[0x4b]	1414948	1			T1	7		T3	29		T60	6
valid_sources[0x4c]	3580179	1			T1	6		T3	46		T60	4
valid_sources[0x4d]	1411773	1			T1	12		T3	32		T60	10
valid_sources[0x4e]	2315776	1			T1	8		T2	30		T3	32
valid_sources[0x4f]	1606299	1			T1	15		T3	45		T60	5
valid_sources[0x50]	1409184	1			T1	8		T3	74		T60	9
valid_sources[0x51]	1413195	1			T1	9		T3	47		T60	3
valid_sources[0x52]	1422037	1			T1	21		T3	82		T60	2
valid_sources[0x53]	1428319	1			T1	13		T3	23		T60	6
valid_sources[0x54]	1420594	1			T1	10		T3	27		T62	1
valid_sources[0x55]	1417156	1			T1	14		T3	24		T60	3
valid_sources[0x56]	1409357	1			T1	8		T3	6		T60	3
valid_sources[0x57]	2266470	1			T1	8		T3	8		T60	1
valid_sources[0x58]	2188752	1			T1	8		T3	7		T60	12
valid_sources[0x59]	1412371	1			T1	8		T3	23		T60	6
valid_sources[0x5a]	2286308	1			T1	12		T3	46		T60	4
valid_sources[0x5b]	1420087	1			T1	10		T3	43		T60	3
valid_sources[0x5c]	1466248	1			T1	15		T3	43		T60	2
valid_sources[0x5d]	1410084	1			T1	8		T3	8		T60	15
valid_sources[0x5e]	1419283	1			T1	11		T3	28		T60	7
valid_sources[0x5f]	1417856	1			T1	6		T3	6		T60	9
valid_sources[0x60]	1415134	1			T1	9		T3	16		T60	8
valid_sources[0x61]	1433357	1			T1	5		T3	22		T60	6
valid_sources[0x62]	4671035	1			T1	11		T3	36		T60	3
valid_sources[0x63]	1412437	1			T1	19		T3	19		T60	8
valid_sources[0x64]	1653021	1			T1	11		T3	2		T60	7
valid_sources[0x65]	1517371	1			T1	9		T3	22		T60	6
valid_sources[0x66]	1479958	1			T1	9		T3	45		T60	6
valid_sources[0x67]	1406380	1			T1	8		T3	32		T60	5
valid_sources[0x68]	1422840	1			T1	16		T3	58		T60	6
valid_sources[0x69]	2320192	1			T1	15		T3	15		T60	6
valid_sources[0x6a]	1454336	1			T1	16		T3	14		T60	12
valid_sources[0x6b]	1409040	1			T1	6		T3	30		T60	9
valid_sources[0x6c]	1498398	1			T1	12		T3	2		T60	6
valid_sources[0x6d]	1404560	1			T1	20		T3	32		T60	6
valid_sources[0x6e]	1450596	1			T1	8		T3	19		T60	8
valid_sources[0x6f]	1421610	1			T1	6		T3	11		T60	3
valid_sources[0x70]	2592818	1			T1	17		T3	65		T60	4
valid_sources[0x71]	2860586	1			T1	4		T3	19		T60	5
valid_sources[0x72]	1422580	1			T1	8		T3	26		T60	5
valid_sources[0x73]	1453430	1			T1	7		T3	7		T60	3
valid_sources[0x74]	1412934	1			T1	9		T3	20		T59	38
valid_sources[0x75]	1551645	1			T1	10		T3	37		T60	9
valid_sources[0x76]	3378331	1			T1	4		T3	17		T60	7
valid_sources[0x77]	1578548	1			T1	11		T3	49		T60	6
valid_sources[0x78]	1414816	1			T1	9		T3	36		T60	4
valid_sources[0x79]	2080296	1			T1	14		T3	28		T60	10
valid_sources[0x7a]	1408986	1			T1	9		T3	22		T60	4
valid_sources[0x7b]	1861189	1			T1	14		T3	31		T60	5
valid_sources[0x7c]	1417511	1			T1	14		T3	15		T60	2
valid_sources[0x7d]	1409019	1			T1	8		T3	18		T60	7
valid_sources[0x7e]	1721815	1			T1	11		T3	23		T60	5
valid_sources[0x7f]	2298497	1			T1	11		T3	27		T60	4
valid_sources[0x80]	1407697	1			T1	8		T3	57		T60	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73213442

1

T1

735

T2

63

T3

3458

values[0x0]

all_enables

biggest_size

62495689

1

T1

574

T2

66

T3

49

values[0x1]

all_enables

biggest_size

53970114

1

T1

542

T2

49

T3

60