Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

271695225

1

T1

887

T2

65

T3

3398

full_word

190190366

1

T1

1851

T2

178

T3

3567

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	461885301	1			T1	2718		T2	243		T3	6965
auto[TlIntgErrCmd]	92	1			T1	4		T65	4		T118	5
auto[TlIntgErrData]	93	1			T1	9		T65	10		T118	3
auto[TlIntgErrBoth]	105	1			T1	7		T65	6		T118	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236115978

1

T1

1526

T2

121

T3

6845

auto[1]

225769613

1

T1

1212

T2

122

T3

120

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	162774428	1			T1	783		T2	58		T3	3387
auto[TlIntgErrNone]	partial	auto[1]	108920535	1			T1	86		T2	7		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	73341428	1			T1	735		T2	63		T3	3458
auto[TlIntgErrNone]	full_word	auto[1]	116848910	1			T1	1114		T2	115		T3	109
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T1	2		T118	2		T121	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T1	2		T65	3		T118	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T65	1		T121	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T118	1		T121	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T1	3		T65	5		T118	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T1	4		T65	5		T118	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T118	1		T163	1		T137	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T1	2		T137	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T1	3		T65	2		T118	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T1	4		T65	2		T121	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T65	1		T122	1		T164	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T65	1		T118	1		T121	1