Module Definition
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Module : kmac_msgfifo
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 100.00 92.86 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_msgfifo 98.21 100.00 100.00 92.86 100.00



Module Instance : tb.dut.u_msgfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 100.00 92.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.32 100.00 95.16 94.52 100.00 94.23 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.56 98.77 96.05 100.00 100.00 96.55 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_msgfifo 98.38 100.00 91.89 100.00 100.00 100.00
u_packer 96.41 100.00 100.00 89.74 92.31 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : kmac_msgfifo
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN13811100.00
ALWAYS14033100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17911100.00
ALWAYS18533100.00
ALWAYS1931616100.00
CONT_ASSIGN23811100.00
ALWAYS24255100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
140 1 1
141 1 1
142 1 1
171 1 1
172 1 1
174 1 1
175 1 1
176 1 1
177 1 1
179 1 1
185 1 1
186 1 1
188 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
207 1 1
208 1 1
210 1 1
215 1 1
216 1 1
218 1 1
220 1 1
225 1 1
226 1 1
228 1 1
238 1 1
242 1 1
249 1 1
250 1 1
256 1 1
257 1 1
MISSING_ELSE


FSM Coverage for Module : kmac_msgfifo
Summary for FSM :: flush_st
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: flush_st
statesLine No.CoveredTests
FlushClear 216 Covered T1
FlushFifo 208 Covered T1
FlushIdle 202 Covered T1
FlushPacker 200 Covered T1


transitionsLine No.CoveredTests
FlushClear->FlushIdle 226 Covered T1
FlushFifo->FlushClear 216 Covered T1
FlushIdle->FlushPacker 200 Covered T1
FlushPacker->FlushFifo 208 Covered T1



Branch Coverage for Module : kmac_msgfifo
Line No.TotalCoveredPercent
Branches 14 13 92.86
IF 185 2 2 100.00
CASE 197 9 8 88.89
IF 249 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 185 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 197 case (flush_st) -2-: 199 if (process_i) -3-: 207 if (packer_flush_done) -4-: 215 if (fifo_empty_o) -5-: 225 if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))

Branches:
-1--2--3--4--5-StatusTests
FlushIdle 1 - - - Covered T4,T5,T6
FlushIdle 0 - - - Covered T4,T5,T6
FlushPacker - 1 - - Covered T4,T5,T6
FlushPacker - 0 - - Covered T4,T5,T6
FlushFifo - - 1 - Covered T4,T5,T6
FlushFifo - - 0 - Covered T4,T5,T6
FlushClear - - - 1 Covered T4,T5,T6
FlushClear - - - 0 Covered T4,T5,T6
default - - - - Not Covered


LineNo. Expression -1-: 249 if (packer_err) -2-: 256 if (fifo_err)

Branches:
-1--2-StatusTests
1 - Covered T7,T8,T9
0 1 Covered T7,T8,T9
0 0 Covered T4,T5,T6


Assert Coverage for Module : kmac_msgfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FlushStInValid_A 2147483647 2147483647 0 0
MessageValid_a 2147483647 110245555 0 0
PackerDoneDelay_A 2147483647 2147483647 0 0
PackerDoneValid_a 2147483647 350544 0 0


FlushStInValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 149799 149790 0 0
T5 205696 205690 0 0
T6 608761 608752 0 0
T10 419387 419289 0 0
T11 153221 153213 0 0
T12 1644 1492 0 0
T34 627816 627807 0 0
T35 193791 193783 0 0
T36 2488 2406 0 0
T37 228135 228125 0 0

MessageValid_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110245555 0 0
T4 149799 19738 0 0
T5 205696 221875 0 0
T6 608761 205891 0 0
T10 419387 11797 0 0
T11 153221 19598 0 0
T12 1644 3 0 0
T34 627816 212387 0 0
T35 193791 209015 0 0
T36 2488 0 0 0
T37 228135 77246 0 0
T47 0 107169 0 0

PackerDoneDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 149799 149790 0 0
T5 205696 205690 0 0
T6 608761 608752 0 0
T10 419387 419289 0 0
T11 153221 153213 0 0
T12 1644 1492 0 0
T34 627816 627807 0 0
T35 193791 193783 0 0
T36 2488 2406 0 0
T37 228135 228125 0 0

PackerDoneValid_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 350544 0 0
T4 149799 137 0 0
T5 205696 390 0 0
T6 608761 374 0 0
T10 419387 96 0 0
T11 153221 133 0 0
T12 1644 0 0 0
T34 627816 374 0 0
T35 193791 374 0 0
T36 2488 0 0 0
T37 228135 48 0 0
T38 0 2265 0 0
T47 0 246 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%