Unified Coverage Report :: Module :: kmac_entropy

Module : kmac_entropy

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.15	100.00	95.74		80.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_entropy.u_entropy	99.15	100.00	95.74		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_entropy.u_entropy

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.15	100.00	95.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	100.00	95.74	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lfsrs[0].u_lfsr_chunk	100.00			100.00
gen_lfsrs[10].u_lfsr_chunk	100.00			100.00
gen_lfsrs[11].u_lfsr_chunk	100.00			100.00
gen_lfsrs[12].u_lfsr_chunk	100.00			100.00
gen_lfsrs[13].u_lfsr_chunk	100.00			100.00
gen_lfsrs[14].u_lfsr_chunk	100.00			100.00
gen_lfsrs[15].u_lfsr_chunk	100.00			100.00
gen_lfsrs[16].u_lfsr_chunk	100.00			100.00
gen_lfsrs[17].u_lfsr_chunk	100.00			100.00
gen_lfsrs[18].u_lfsr_chunk	100.00			100.00
gen_lfsrs[19].u_lfsr_chunk	100.00			100.00
gen_lfsrs[1].u_lfsr_chunk	100.00			100.00
gen_lfsrs[20].u_lfsr_chunk	100.00			100.00
gen_lfsrs[21].u_lfsr_chunk	100.00			100.00
gen_lfsrs[22].u_lfsr_chunk	100.00			100.00
gen_lfsrs[23].u_lfsr_chunk	100.00			100.00
gen_lfsrs[24].u_lfsr_chunk	100.00			100.00
gen_lfsrs[2].u_lfsr_chunk	100.00			100.00
gen_lfsrs[3].u_lfsr_chunk	100.00			100.00
gen_lfsrs[4].u_lfsr_chunk	100.00			100.00
gen_lfsrs[5].u_lfsr_chunk	100.00			100.00
gen_lfsrs[6].u_lfsr_chunk	100.00			100.00
gen_lfsrs[7].u_lfsr_chunk	100.00			100.00
gen_lfsrs[8].u_lfsr_chunk	100.00			100.00
gen_lfsrs[9].u_lfsr_chunk	100.00			100.00
u_entropy_configured	100.00	100.00				100.00	100.00
u_hash_count	100.00			100.00
u_seed_idx_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
TOTAL		1610	1610	100.00
ALWAYS	241	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	259	8	8	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	6	6	100.00
ALWAYS	284	8	8	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
ALWAYS	339	6	6	100.00
ALWAYS	345	4	4	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
ALWAYS	465	3	3	100.00
CONT_ASSIGN	475	1	1	100.00
ALWAYS	480	3	3	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
ALWAYS	495	6	6	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
ALWAYS	526	3	3	100.00
CONT_ASSIGN	536	1	1	100.00
ALWAYS	545	3	3	100.00
ALWAYS	550	78	78	100.00
ALWAYS	788	3	3	100.00
CONT_ASSIGN	797	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
241	1	1
242	1	1
243	1	1
244	1	1
			MISSING_ELSE
250	1	1
251	1	1
252	1	1
253	1	1
			MISSING_ELSE
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
266	1	1
			MISSING_ELSE
270	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
295	1	1
304	2	2
305	1	1
308	1	1
311	1	1
314	1	1
336	1	1
339	2	2
340	2	2
341	2	2
			MISSING_ELSE
345	2	2
346	2	2
			MISSING_ELSE
392	1	1
400	5	5
408	5	5
414	640	640
451	1	1
453	800	800
457	1	1
462	1	1
465	1	1
466	1	1
468	1	1
475	1	1
480	1	1
481	1	1
483	1	1
490	1	1
491	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
			MISSING_ELSE
505	1	1
523	1	1
524	1	1
526	1	1
527	1	1
529	1	1
536	1	1
545	3	3
550	1	1
551	1	1
554	1	1
555	1	1
557	1	1
560	1	1
568	1	1
569	1	1
572	1	1
576	1	1
580	1	1
583	1	1
586	1	1
589	1	1
591	1	1
593	1	1
596	1	1
598	1	1
600	1	1
602	1	1
606	1	1
609	1	1
619	1	1
624	1	1
629	1	1
631	1	1
633	1	1
642	1	1
643	1	1
645	1	1
646	1	1
648	1	1
650	1	1
652	1	1
654	1	1
657	1	1
660	1	1
662	1	1
668	1	1
671	1	1
673	1	1
675	1	1
677	1	1
678	1	1
680	1	1
681	1	1
683	1	1
684	1	1
685	1	1
			MISSING_ELSE
688	1	1
690	1	1
697	1	1
699	1	1
700	1	1
702	1	1
707	1	1
709	1	1
710	1	1
712	1	1
714	1	1
716	1	1
722	1	1
726	1	1
727	1	1
729	1	1
733	1	1
735	1	1
742	1	1
744	1	1
752	1	1
755	1	1
757	1	1
758	1	1
761	1	1
768	1	1
769	1	1
781	1	1
782	1	1
			MISSING_ELSE
788	1	1
789	1	1
791	1	1
797	1	1

---

Cond Coverage for Module : kmac_entropy

	Total	Covered	Percent
Conditions	188	180	95.74
Logical	188	180	95.74
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T34
1	1	0	Covered	T6,T10,T47
1	1	1	Covered	T4,T5,T34

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T34
1	1	Covered	T6,T34,T10

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T34
1	Covered	T4,T5,T6

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T34
1	1	Covered	T4,T5,T6

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T34
1	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T34
1	1	Covered	T4,T5,T6

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T18,T80,T19
0	1	0	Covered	T16,T19,T58
1	0	0	Covered	T16,T18,T80

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T10,T11
1	1	Covered	T4,T10,T11

 LINE       336
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T19,T58

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[0] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[1] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[2] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[3] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[4] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       462
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       475
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 2)-:4] : ({1'b0, lfsr_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       523
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T81,T82,T83
1	0	Covered	T4,T5,T34

 LINE       524
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T34
1	1	Covered	T4,T5,T34

 LINE       524
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T34
1	0	Covered	T81,T82,T83

 LINE       536
 EXPRESSION (hash_count_error | seed_idx_count_error)
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       633
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       633
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T10,T11

 LINE       633
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T10,T11

 LINE       652
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T80
1	0	Covered	T4,T5,T34
1	1	Covered	T18,T44,T21

 LINE       652
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Covered	T6,T10,T47
1	Covered	T4,T5,T34

 LINE       652
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T19,T58
1	0	Covered	T18,T80,T57

 LINE       673
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T34
1	0	Covered	T35,T84,T42
1	1	Covered	T81,T85,T86

 LINE       683
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T42,T29
0	1	Covered	T4,T34,T11
1	0	Covered	T44,T45

 LINE       683
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T42,T29
1	1	Covered	T44,T45

 LINE       690
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T34,T11
1	0	Covered	T44,T87,T45
1	1	Covered	T44,T45,T46

 LINE       690
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T42,T29
0	1	Covered	T4,T34,T11
1	0	Covered	T44,T45

 LINE       690
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T42,T29
1	1	Covered	T44,T45

 LINE       755
 EXPRESSION (rand_consumed_i & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             -------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T81,T88
1	0	Not Covered
1	1	Not Covered

 LINE       755
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T88,T89
0	1	Covered	T36,T81,T88
1	0	Not Covered

 LINE       755
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T36,T88,T89
1	1	Not Covered

 LINE       797
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       797
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Module : kmac_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	20	16	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	606	Covered	T1
StRandErr	733	Covered	T1
StRandErrIncorrectMode	615	Covered	T1
StRandErrWaitExpired	675	Covered	T1
StRandGenerate	646	Covered	T1
StRandReady	650	Covered	T1
StRandReset	619	Covered	T1
StSwSeedWait	602	Covered	T1
StTerminalError	782	Covered	T1

transitions	Line No.	Covered	Tests
StRandEdn->StRandErrWaitExpired	675	Covered	T1
StRandEdn->StRandGenerate	681	Covered	T1
StRandEdn->StTerminalError	782	Covered	T1
StRandErr->StRandReset	758	Covered	T1
StRandErr->StTerminalError	782	Not Covered
StRandErrIncorrectMode->StRandErr	742	Covered	T1
StRandErrIncorrectMode->StTerminalError	782	Not Covered
StRandErrWaitExpired->StRandErr	733	Covered	T1
StRandErrWaitExpired->StTerminalError	782	Not Covered
StRandGenerate->StRandReady	729	Covered	T1
StRandGenerate->StTerminalError	782	Covered	T1
StRandReady->StRandEdn	654	Covered	T1
StRandReady->StRandGenerate	646	Covered	T1
StRandReady->StTerminalError	782	Covered	T1
StRandReset->StRandEdn	606	Covered	T1
StRandReset->StRandErrIncorrectMode	615	Covered	T1
StRandReset->StSwSeedWait	602	Covered	T1
StRandReset->StTerminalError	782	Covered	T1
StSwSeedWait->StRandGenerate	710	Covered	T1
StSwSeedWait->StTerminalError	782	Not Covered

---

Branch Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
Branches		84	84	100.00
TERNARY	462	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	797	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	408	2	2	100.00
IF	241	3	3	100.00
IF	250	3	3	100.00
IF	259	5	5	100.00
IF	273	4	4	100.00
IF	284	5	5	100.00
IF	304	2	2	100.00
IF	339	4	4	100.00
IF	345	3	3	100.00
IF	465	2	2	100.00
IF	480	2	2	100.00
IF	495	4	4	100.00
IF	526	2	2	100.00
IF	545	2	2	100.00
CASE	591	23	23	100.00
IF	781	2	2	100.00
IF	788	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	462	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	475	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	797	((st != StRandReset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	if ((!rst_ni))
-2-:	243	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T34
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T34
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	259	if ((!rst_ni))
-2-:	261	if (timer_update)
-3-:	263	if (timer_expired)
-4-:	265	if (((timer_enable && timer_pulse) && (|timer_value)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T34
0	0	1	-	Covered	T6,T34,T10
0	0	0	1	Covered	T4,T5,T34
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (timer_update)
-3-:	277	if ((timer_enable && (timer_value == '0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T34
0	0	1	Covered	T6,T34,T10
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	286	if (timer_update)
-3-:	288	if ((timer_enable && (prescaler_cnt == '0)))
-4-:	290	if (timer_enable)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T34
0	0	1	-	Covered	T4,T5,T6
0	0	0	1	Covered	T4,T5,T34
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	339	if ((!rst_ni))
-2-:	340	if (threshold_hit_clr)
-3-:	341	if (threshold_hit)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T18,T44,T21
0	0	1	Covered	T16,T19,T58
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	345	if ((!rst_ni))
-2-:	346	if (mode_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	465	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	480	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	495	if ((!rst_ni))
-2-:	497	if (rand_valid_set)
-3-:	499	if (rand_valid_clear)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	526	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	545	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	591	case (st)
-2-:	593	if (entropy_ready_i)
-3-:	600	case (mode_i)
-4-:	633	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-5-:	645	if (ready_phase_q)
-6-:	652	if (((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q)))
-7-:	673	if ((timer_expired && non_zero_wait_timer_limit))
-8-:	677	if (entropy_ack_i)
-9-:	680	if (lfsr_seed_done)
-10-:	683	if (((fast_process_i && in_keyblock_i) || (!fast_process_i)))
-11-:	690	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-12-:	709	if (lfsr_seed_done)
-13-:	757	if (err_processed_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T47
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T34
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Covered	T36,T88,T89
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T18,T44,T21
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T81,T85,T86
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T4,T34,T11
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T5,T42,T29
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T4,T5,T34
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Covered	T44,T45,T46
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Covered	T4,T5,T34
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T10,T47
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T6,T10,T47
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T81,T85,T86
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T36,T88,T89
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T36,T81,T88
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T36,T81,T88
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	781	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	788	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : kmac_entropy

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ChunkSizeEntropyLfsrMatchesEdn	1055	1055	0	0
ChunkSizeEntropyLfsrMatchesSw	1055	1055	0	0
ConsumeNotAssertWhenNotValid_M	2147483647	157028862	0	0
EntropyLfsrWDivisble	1055	1055	0	0
ModeKnown_A	2147483647	2147483647	0	0
RandStKnown_A	2147483647	2147483647	0	0
p_perm_check.PermutationCheck_A	1055	1055	0	0
p_perm_fwd_check.PermutationCheck_A	1055	1055	0	0
u_state_regs_A	2147483647	2147483647	0	0

ChunkSizeEntropyLfsrMatchesEdn

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ChunkSizeEntropyLfsrMatchesSw

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ConsumeNotAssertWhenNotValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	157028862	0	0
T4	149799	60384	0	0
T5	205696	266016	0	0
T6	608761	265248	0	0
T10	419387	34992	0	0
T11	153221	57888	0	0
T12	1644	48	0	0
T34	627816	265248	0	0
T35	193791	265248	0	0
T36	2488	0	0	0
T37	228135	99984	0	0
T47	0	260496	0	0

EntropyLfsrWDivisble

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	149799	149790	0	0
T5	205696	205690	0	0
T6	608761	608752	0	0
T10	419387	419289	0	0
T11	153221	153213	0	0
T12	1644	1492	0	0
T34	627816	627807	0	0
T35	193791	193783	0	0
T36	2488	2406	0	0
T37	228135	228125	0	0

RandStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	149799	149790	0	0
T5	205696	205690	0	0
T6	608761	608752	0	0
T10	419387	419289	0	0
T11	153221	153213	0	0
T12	1644	1492	0	0
T34	627816	627807	0	0
T35	193791	193783	0	0
T36	2488	2406	0	0
T37	228135	228125	0	0

p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

p_perm_fwd_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	149799	149790	0	0
T5	205696	205690	0	0
T6	608761	608752	0	0
T10	419387	419289	0	0
T11	153221	153213	0	0
T12	1644	1492	0	0
T34	627816	627807	0	0
T35	193791	193783	0	0
T36	2488	2406	0	0
T37	228135	228125	0	0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
TOTAL		1610	1610	100.00
ALWAYS	241	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	259	8	8	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	6	6	100.00
ALWAYS	284	8	8	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
ALWAYS	339	6	6	100.00
ALWAYS	345	4	4	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
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CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
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CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
ALWAYS	465	3	3	100.00
CONT_ASSIGN	475	1	1	100.00
ALWAYS	480	3	3	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
ALWAYS	495	6	6	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
ALWAYS	526	3	3	100.00
CONT_ASSIGN	536	1	1	100.00
ALWAYS	545	3	3	100.00
ALWAYS	550	78	78	100.00
ALWAYS	788	3	3	100.00
CONT_ASSIGN	797	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
241	1	1
242	1	1
243	1	1
244	1	1
			MISSING_ELSE
250	1	1
251	1	1
252	1	1
253	1	1
			MISSING_ELSE
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
266	1	1
			MISSING_ELSE
270	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
295	1	1
304	2	2
305	1	1
308	1	1
311	1	1
314	1	1
336	1	1
339	2	2
340	2	2
341	2	2
			MISSING_ELSE
345	2	2
346	2	2
			MISSING_ELSE
392	1	1
400	5	5
408	5	5
414	640	640
451	1	1
453	800	800
457	1	1
462	1	1
465	1	1
466	1	1
468	1	1
475	1	1
480	1	1
481	1	1
483	1	1
490	1	1
491	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
			MISSING_ELSE
505	1	1
523	1	1
524	1	1
526	1	1
527	1	1
529	1	1
536	1	1
545	3	3
550	1	1
551	1	1
554	1	1
555	1	1
557	1	1
560	1	1
568	1	1
569	1	1
572	1	1
576	1	1
580	1	1
583	1	1
586	1	1
589	1	1
591	1	1
593	1	1
596	1	1
598	1	1
600	1	1
602	1	1
606	1	1
609	1	1
619	1	1
624	1	1
629	1	1
631	1	1
633	1	1
642	1	1
643	1	1
645	1	1
646	1	1
648	1	1
650	1	1
652	1	1
654	1	1
657	1	1
660	1	1
662	1	1
668	1	1
671	1	1
673	1	1
675	1	1
677	1	1
678	1	1
680	1	1
681	1	1
683	1	1
684	1	1
685	1	1
			MISSING_ELSE
688	1	1
690	1	1
697	1	1
699	1	1
700	1	1
702	1	1
707	1	1
709	1	1
710	1	1
712	1	1
714	1	1
716	1	1
722	1	1
726	1	1
727	1	1
729	1	1
733	1	1
735	1	1
742	1	1
744	1	1
752	1	1
755	1	1
757	1	1
758	1	1
761	1	1
768	1	1
769	1	1
781	1	1
782	1	1
			MISSING_ELSE
788	1	1
789	1	1
791	1	1
797	1	1

---

Cond Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Total	Covered	Percent
Conditions	188	180	95.74
Logical	188	180	95.74
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T34
1	1	0	Covered	T6,T10,T47
1	1	1	Covered	T4,T5,T34

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T34
1	1	Covered	T6,T34,T10

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T34
1	Covered	T4,T5,T6

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T34
1	1	Covered	T4,T5,T6

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T34
1	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T34
1	1	Covered	T4,T5,T6

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T18,T80,T19
0	1	0	Covered	T16,T19,T58
1	0	0	Covered	T16,T18,T80

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T10,T11
1	1	Covered	T4,T10,T11

 LINE       336
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T19,T58

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[0] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[1] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[2] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[3] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[4] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T10,T47

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       462
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       475
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 2)-:4] : ({1'b0, lfsr_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       523
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T81,T82,T83
1	0	Covered	T4,T5,T34

 LINE       524
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T34
1	1	Covered	T4,T5,T34

 LINE       524
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T34
1	0	Covered	T81,T82,T83

 LINE       536
 EXPRESSION (hash_count_error | seed_idx_count_error)
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       633
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       633
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T10,T11

 LINE       633
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T10,T11

 LINE       652
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T80
1	0	Covered	T4,T5,T34
1	1	Covered	T18,T44,T21

 LINE       652
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Covered	T6,T10,T47
1	Covered	T4,T5,T34

 LINE       652
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T19,T58
1	0	Covered	T18,T80,T57

 LINE       673
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T34
1	0	Covered	T35,T84,T42
1	1	Covered	T81,T85,T86

 LINE       683
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T42,T29
0	1	Covered	T4,T34,T11
1	0	Covered	T44,T45

 LINE       683
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T42,T29
1	1	Covered	T44,T45

 LINE       690
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T34,T11
1	0	Covered	T44,T87,T45
1	1	Covered	T44,T45,T46

 LINE       690
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T42,T29
0	1	Covered	T4,T34,T11
1	0	Covered	T44,T45

 LINE       690
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T42,T29
1	1	Covered	T44,T45

 LINE       755
 EXPRESSION (rand_consumed_i & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             -------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T81,T88
1	0	Not Covered
1	1	Not Covered

 LINE       755
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T88,T89
0	1	Covered	T36,T81,T88
1	0	Not Covered

 LINE       755
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T36,T88,T89
1	1	Not Covered

 LINE       797
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       797
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_entropy.u_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	16	16	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	606	Covered	T1
StRandErr	733	Covered	T1
StRandErrIncorrectMode	615	Covered	T1
StRandErrWaitExpired	675	Covered	T1
StRandGenerate	646	Covered	T1
StRandReady	650	Covered	T1
StRandReset	619	Covered	T1
StSwSeedWait	602	Covered	T1
StTerminalError	782	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
StRandEdn->StRandErrWaitExpired	675	Covered	T1
StRandEdn->StRandGenerate	681	Covered	T1
StRandEdn->StTerminalError	782	Covered	T1
StRandErr->StRandReset	758	Covered	T1
StRandErr->StTerminalError	782	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrIncorrectMode->StRandErr	742	Covered	T1
StRandErrIncorrectMode->StTerminalError	782	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrWaitExpired->StRandErr	733	Covered	T1
StRandErrWaitExpired->StTerminalError	782	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandGenerate->StRandReady	729	Covered	T1
StRandGenerate->StTerminalError	782	Covered	T1
StRandReady->StRandEdn	654	Covered	T1
StRandReady->StRandGenerate	646	Covered	T1
StRandReady->StTerminalError	782	Covered	T1
StRandReset->StRandEdn	606	Covered	T1
StRandReset->StRandErrIncorrectMode	615	Covered	T1
StRandReset->StSwSeedWait	602	Covered	T1
StRandReset->StTerminalError	782	Covered	T1
StSwSeedWait->StRandGenerate	710	Covered	T1
StSwSeedWait->StTerminalError	782	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.

---

Branch Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
Branches		84	84	100.00
TERNARY	462	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	797	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	408	2	2	100.00
IF	241	3	3	100.00
IF	250	3	3	100.00
IF	259	5	5	100.00
IF	273	4	4	100.00
IF	284	5	5	100.00
IF	304	2	2	100.00
IF	339	4	4	100.00
IF	345	3	3	100.00
IF	465	2	2	100.00
IF	480	2	2	100.00
IF	495	4	4	100.00
IF	526	2	2	100.00
IF	545	2	2	100.00
CASE	591	23	23	100.00
IF	781	2	2	100.00
IF	788	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	462	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	475	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	797	((st != StRandReset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	if ((!rst_ni))
-2-:	243	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T34
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T34
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	259	if ((!rst_ni))
-2-:	261	if (timer_update)
-3-:	263	if (timer_expired)
-4-:	265	if (((timer_enable && timer_pulse) && (|timer_value)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T34
0	0	1	-	Covered	T6,T34,T10
0	0	0	1	Covered	T4,T5,T34
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (timer_update)
-3-:	277	if ((timer_enable && (timer_value == '0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T34
0	0	1	Covered	T6,T34,T10
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	286	if (timer_update)
-3-:	288	if ((timer_enable && (prescaler_cnt == '0)))
-4-:	290	if (timer_enable)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T34
0	0	1	-	Covered	T4,T5,T6
0	0	0	1	Covered	T4,T5,T34
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	339	if ((!rst_ni))
-2-:	340	if (threshold_hit_clr)
-3-:	341	if (threshold_hit)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T18,T44,T21
0	0	1	Covered	T16,T19,T58
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	345	if ((!rst_ni))
-2-:	346	if (mode_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	465	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	480	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	495	if ((!rst_ni))
-2-:	497	if (rand_valid_set)
-3-:	499	if (rand_valid_clear)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	526	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	545	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	591	case (st)
-2-:	593	if (entropy_ready_i)
-3-:	600	case (mode_i)
-4-:	633	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-5-:	645	if (ready_phase_q)
-6-:	652	if (((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q)))
-7-:	673	if ((timer_expired && non_zero_wait_timer_limit))
-8-:	677	if (entropy_ack_i)
-9-:	680	if (lfsr_seed_done)
-10-:	683	if (((fast_process_i && in_keyblock_i) || (!fast_process_i)))
-11-:	690	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-12-:	709	if (lfsr_seed_done)
-13-:	757	if (err_processed_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T47
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T34
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Covered	T36,T88,T89
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T18,T44,T21
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T81,T85,T86
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T4,T34,T11
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T5,T42,T29
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T4,T5,T34
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Covered	T44,T45,T46
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Covered	T4,T5,T34
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T10,T47
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T6,T10,T47
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T81,T85,T86
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T36,T88,T89
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T36,T81,T88
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T36,T81,T88
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	781	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	788	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ChunkSizeEntropyLfsrMatchesEdn	1055	1055	0	0
ChunkSizeEntropyLfsrMatchesSw	1055	1055	0	0
ConsumeNotAssertWhenNotValid_M	2147483647	157028862	0	0
EntropyLfsrWDivisble	1055	1055	0	0
ModeKnown_A	2147483647	2147483647	0	0
RandStKnown_A	2147483647	2147483647	0	0
p_perm_check.PermutationCheck_A	1055	1055	0	0
p_perm_fwd_check.PermutationCheck_A	1055	1055	0	0
u_state_regs_A	2147483647	2147483647	0	0

ChunkSizeEntropyLfsrMatchesEdn

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ChunkSizeEntropyLfsrMatchesSw

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ConsumeNotAssertWhenNotValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	157028862	0	0
T4	149799	60384	0	0
T5	205696	266016	0	0
T6	608761	265248	0	0
T10	419387	34992	0	0
T11	153221	57888	0	0
T12	1644	48	0	0
T34	627816	265248	0	0
T35	193791	265248	0	0
T36	2488	0	0	0
T37	228135	99984	0	0
T47	0	260496	0	0

EntropyLfsrWDivisble

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	149799	149790	0	0
T5	205696	205690	0	0
T6	608761	608752	0	0
T10	419387	419289	0	0
T11	153221	153213	0	0
T12	1644	1492	0	0
T34	627816	627807	0	0
T35	193791	193783	0	0
T36	2488	2406	0	0
T37	228135	228125	0	0

RandStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	149799	149790	0	0
T5	205696	205690	0	0
T6	608761	608752	0	0
T10	419387	419289	0	0
T11	153221	153213	0	0
T12	1644	1492	0	0
T34	627816	627807	0	0
T35	193791	193783	0	0
T36	2488	2406	0	0
T37	228135	228125	0	0

p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

p_perm_fwd_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	149799	149790	0	0
T5	205696	205690	0	0
T6	608761	608752	0	0
T10	419387	419289	0	0
T11	153221	153213	0	0
T12	1644	1492	0	0
T34	627816	627807	0	0
T35	193791	193783	0	0
T36	2488	2406	0	0
T37	228135	228125	0	0