Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	116903167	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	116903167	0	0
T62	2340	197	0	0
T63	11566	509	0	0
T64	1519	0	0	0
T65	19513	0	0	0
T66	3627	372	0	0
T67	1399	0	0	0
T68	1486	366	0	0
T69	0	32	0	0
T70	0	1070	0	0
T71	0	183	0	0
T72	0	28	0	0
T73	0	291	0	0
T75	2071	0	0	0
T76	3138	0	0	0
T77	1331	0	0	0
T78	0	517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	207445470	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	207445470	0	0
T62	2340	163	0	0
T63	11566	1756	0	0
T64	1519	0	0	0
T65	19513	0	0	0
T66	3627	294	0	0
T67	1399	0	0	0
T68	1486	192	0	0
T69	0	31	0	0
T70	0	596	0	0
T71	0	761	0	0
T72	0	28	0	0
T73	0	235	0	0
T75	2071	0	0	0
T76	3138	0	0	0
T77	1331	0	0	0
T78	0	269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	328402520	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328402520	0	0
T1	9939	5316	0	0
T2	1599	481	0	0
T3	15920	13813	0	0
T59	1187	38	0	0
T60	10355	1631	0	0
T61	768	22	0	0
T62	2340	544	0	0
T63	11566	1069	0	0
T64	1519	40	0	0
T65	19513	2888	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	596630147	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	596630147	0	0
T1	9939	2738	0	0
T2	1599	243	0	0
T3	15920	6965	0	0
T59	1187	181	0	0
T60	10355	1436	0	0
T61	768	22	0	0
T62	2340	340	0	0
T63	11566	3072	0	0
T64	1519	125	0	0
T65	19513	2677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9939	8440	0	0
T2	1599	1351	0	0
T3	15920	15869	0	0
T59	1187	1104	0	0
T60	10355	9861	0	0
T61	768	673	0	0
T62	2340	2282	0	0
T63	11566	11489	0	0
T64	1519	1465	0	0
T65	19513	17937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0