Unified Coverage Report :: Module :: keccak_2share

Module : keccak_2share

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.23	100.00	98.75			98.17	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p	99.23	100.00	98.75			98.17	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.23	100.00	98.75			98.17	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.30	100.00	98.75			98.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.32	92.94	100.00		73.33	90.32	100.00	u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_2share_chi.g_chi_w[0].u_dom	100.00	100.00				100.00	100.00
g_2share_chi.g_chi_w[1].u_dom	100.00	100.00				100.00	100.00
g_2share_chi.g_chi_w[2].u_dom	100.00	100.00				100.00	100.00
g_2share_chi.g_chi_w[3].u_dom	100.00	100.00				100.00	100.00
g_2share_chi.g_chi_w[4].u_dom	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
TOTAL		315	315	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	3	3	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	175	3	3	100.00
ALWAYS	205	13	13	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
ROUTINE	440	0	0
ROUTINE	440	5	5	100.00
ROUTINE	453	0	0
ROUTINE	453	5	5	100.00
ROUTINE	466	4	4	100.00
ROUTINE	486	0	0
ROUTINE	486	10	10	100.00
ROUTINE	555	0	0
ROUTINE	555	4	4	100.00
ROUTINE	624	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	2	2
90	2	2
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
132	2	2
136	2	2
143	1	1
147	1	1
148	1	1
171	1	1
175	1	1
176	1	1
178	1	1
205	1	1
207	1	1
208	1	1
209	1	1
212	1	1
213	1	1
214	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
236	1	1
250	5	5
251	5	5
253	5	5
254	5	5
261	5	5
266	5	5
272	5	5
277	5	5
283	5	5
288	5	5
294	5	5
299	5	5
306	5	5
307	5	5
308	5	5
309	5	5
315	5	5
342	5	5
343	5	5
344	5	5
345	5	5
346	5	5
348	5	5
349	5	5
350	5	5
351	5	5
352	5	5
355	5	5
356	5	5
363	25	25
366	25	25
391	2	2
392	2	2
399	2	2
401	48	48
421	1	1
440	1	1
441	1	1
442	1	1
443	1	1
447	1	1
453	1	1
454	1	1
455	1	1
456	1	1
460	1	1
466	1	1
467	1	1
469	1	1
471	1	1
486	1	1
487	1	1
489	1	1
490	1	1
492	1	1
493	1	1
496	1	1
497	1	1
498	1	1
501	1	1
555	1	1
556	1	1
557	1	1
560	1	1
624	1	1
625	1	1
627	1	1

---

Cond Coverage for Module : keccak_2share

	Total	Covered	Percent
Conditions	160	158	98.75
Logical	160	158	98.75
Non-Logical	0	0
Event	0	0

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[0].a0_l : g_2share_chi.g_chi_w[0].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[1].a0_l : g_2share_chi.g_chi_w[1].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[2].a0_l : g_2share_chi.g_chi_w[2].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[3].a0_l : g_2share_chi.g_chi_w[3].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       306
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[4].a0_l : g_2share_chi.g_chi_w[4].a0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[0].a1_l : g_2share_chi.g_chi_w[0].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[1].a1_l : g_2share_chi.g_chi_w[1].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[2].a1_l : g_2share_chi.g_chi_w[2].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[3].a1_l : g_2share_chi.g_chi_w[3].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       307
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[4].a1_l : g_2share_chi.g_chi_w[4].a1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[0].b0_l : g_2share_chi.g_chi_w[0].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[1].b0_l : g_2share_chi.g_chi_w[1].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[2].b0_l : g_2share_chi.g_chi_w[2].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[3].b0_l : g_2share_chi.g_chi_w[3].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       308
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[4].b0_l : g_2share_chi.g_chi_w[4].b0_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[0].b1_l : g_2share_chi.g_chi_w[0].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[1].b1_l : g_2share_chi.g_chi_w[1].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[2].b1_l : g_2share_chi.g_chi_w[2].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[3].b1_l : g_2share_chi.g_chi_w[3].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       309
 EXPRESSION (g_2share_chi.in_data_low ? g_2share_chi.g_chi_w[4].b1_l : g_2share_chi.g_chi_w[4].b1_h)
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(0 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(0, 5)])
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(1 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(1, 5)])
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(2 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(2, 5)])
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(3 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(3, 5)])
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       315
 EXPRESSION (g_2share_chi.in_rand_ext ? rand_i[(4 * g_2share_chi.WSheetHalf)+:g_2share_chi.WSheetHalf] : g_2share_chi.out_prd[keccak_2share.rot_int(4, 5)])
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][0][(W - 1):(W / 2)], iota_data[0][0][0][((W / 2) - 1):0]}) : ({iota_data[0][0][0][(W - 1):(W / 2)], state_in[0][0][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][1][(W - 1):(W / 2)], iota_data[0][0][1][((W / 2) - 1):0]}) : ({iota_data[0][0][1][(W - 1):(W / 2)], state_in[0][0][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][2][(W - 1):(W / 2)], iota_data[0][0][2][((W / 2) - 1):0]}) : ({iota_data[0][0][2][(W - 1):(W / 2)], state_in[0][0][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][3][(W - 1):(W / 2)], iota_data[0][0][3][((W / 2) - 1):0]}) : ({iota_data[0][0][3][(W - 1):(W / 2)], state_in[0][0][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][0][4][(W - 1):(W / 2)], iota_data[0][0][4][((W / 2) - 1):0]}) : ({iota_data[0][0][4][(W - 1):(W / 2)], state_in[0][0][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][0][(W - 1):(W / 2)], iota_data[0][1][0][((W / 2) - 1):0]}) : ({iota_data[0][1][0][(W - 1):(W / 2)], state_in[0][1][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][1][(W - 1):(W / 2)], iota_data[0][1][1][((W / 2) - 1):0]}) : ({iota_data[0][1][1][(W - 1):(W / 2)], state_in[0][1][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][2][(W - 1):(W / 2)], iota_data[0][1][2][((W / 2) - 1):0]}) : ({iota_data[0][1][2][(W - 1):(W / 2)], state_in[0][1][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][3][(W - 1):(W / 2)], iota_data[0][1][3][((W / 2) - 1):0]}) : ({iota_data[0][1][3][(W - 1):(W / 2)], state_in[0][1][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][1][4][(W - 1):(W / 2)], iota_data[0][1][4][((W / 2) - 1):0]}) : ({iota_data[0][1][4][(W - 1):(W / 2)], state_in[0][1][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][0][(W - 1):(W / 2)], iota_data[0][2][0][((W / 2) - 1):0]}) : ({iota_data[0][2][0][(W - 1):(W / 2)], state_in[0][2][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][1][(W - 1):(W / 2)], iota_data[0][2][1][((W / 2) - 1):0]}) : ({iota_data[0][2][1][(W - 1):(W / 2)], state_in[0][2][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][2][(W - 1):(W / 2)], iota_data[0][2][2][((W / 2) - 1):0]}) : ({iota_data[0][2][2][(W - 1):(W / 2)], state_in[0][2][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][3][(W - 1):(W / 2)], iota_data[0][2][3][((W / 2) - 1):0]}) : ({iota_data[0][2][3][(W - 1):(W / 2)], state_in[0][2][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][2][4][(W - 1):(W / 2)], iota_data[0][2][4][((W / 2) - 1):0]}) : ({iota_data[0][2][4][(W - 1):(W / 2)], state_in[0][2][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][0][(W - 1):(W / 2)], iota_data[0][3][0][((W / 2) - 1):0]}) : ({iota_data[0][3][0][(W - 1):(W / 2)], state_in[0][3][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][1][(W - 1):(W / 2)], iota_data[0][3][1][((W / 2) - 1):0]}) : ({iota_data[0][3][1][(W - 1):(W / 2)], state_in[0][3][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][2][(W - 1):(W / 2)], iota_data[0][3][2][((W / 2) - 1):0]}) : ({iota_data[0][3][2][(W - 1):(W / 2)], state_in[0][3][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][3][(W - 1):(W / 2)], iota_data[0][3][3][((W / 2) - 1):0]}) : ({iota_data[0][3][3][(W - 1):(W / 2)], state_in[0][3][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][3][4][(W - 1):(W / 2)], iota_data[0][3][4][((W / 2) - 1):0]}) : ({iota_data[0][3][4][(W - 1):(W / 2)], state_in[0][3][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][0][(W - 1):(W / 2)], iota_data[0][4][0][((W / 2) - 1):0]}) : ({iota_data[0][4][0][(W - 1):(W / 2)], state_in[0][4][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][1][(W - 1):(W / 2)], iota_data[0][4][1][((W / 2) - 1):0]}) : ({iota_data[0][4][1][(W - 1):(W / 2)], state_in[0][4][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][2][(W - 1):(W / 2)], iota_data[0][4][2][((W / 2) - 1):0]}) : ({iota_data[0][4][2][(W - 1):(W / 2)], state_in[0][4][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][3][(W - 1):(W / 2)], iota_data[0][4][3][((W / 2) - 1):0]}) : ({iota_data[0][4][3][(W - 1):(W / 2)], state_in[0][4][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[0][4][4][(W - 1):(W / 2)], iota_data[0][4][4][((W / 2) - 1):0]}) : ({iota_data[0][4][4][(W - 1):(W / 2)], state_in[0][4][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][0][(W - 1):(W / 2)], iota_data[1][0][0][((W / 2) - 1):0]}) : ({iota_data[1][0][0][(W - 1):(W / 2)], state_in[1][0][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][1][(W - 1):(W / 2)], iota_data[1][0][1][((W / 2) - 1):0]}) : ({iota_data[1][0][1][(W - 1):(W / 2)], state_in[1][0][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][2][(W - 1):(W / 2)], iota_data[1][0][2][((W / 2) - 1):0]}) : ({iota_data[1][0][2][(W - 1):(W / 2)], state_in[1][0][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][3][(W - 1):(W / 2)], iota_data[1][0][3][((W / 2) - 1):0]}) : ({iota_data[1][0][3][(W - 1):(W / 2)], state_in[1][0][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][0][4][(W - 1):(W / 2)], iota_data[1][0][4][((W / 2) - 1):0]}) : ({iota_data[1][0][4][(W - 1):(W / 2)], state_in[1][0][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][0][(W - 1):(W / 2)], iota_data[1][1][0][((W / 2) - 1):0]}) : ({iota_data[1][1][0][(W - 1):(W / 2)], state_in[1][1][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][1][(W - 1):(W / 2)], iota_data[1][1][1][((W / 2) - 1):0]}) : ({iota_data[1][1][1][(W - 1):(W / 2)], state_in[1][1][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][2][(W - 1):(W / 2)], iota_data[1][1][2][((W / 2) - 1):0]}) : ({iota_data[1][1][2][(W - 1):(W / 2)], state_in[1][1][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][3][(W - 1):(W / 2)], iota_data[1][1][3][((W / 2) - 1):0]}) : ({iota_data[1][1][3][(W - 1):(W / 2)], state_in[1][1][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][1][4][(W - 1):(W / 2)], iota_data[1][1][4][((W / 2) - 1):0]}) : ({iota_data[1][1][4][(W - 1):(W / 2)], state_in[1][1][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][0][(W - 1):(W / 2)], iota_data[1][2][0][((W / 2) - 1):0]}) : ({iota_data[1][2][0][(W - 1):(W / 2)], state_in[1][2][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][1][(W - 1):(W / 2)], iota_data[1][2][1][((W / 2) - 1):0]}) : ({iota_data[1][2][1][(W - 1):(W / 2)], state_in[1][2][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][2][(W - 1):(W / 2)], iota_data[1][2][2][((W / 2) - 1):0]}) : ({iota_data[1][2][2][(W - 1):(W / 2)], state_in[1][2][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][3][(W - 1):(W / 2)], iota_data[1][2][3][((W / 2) - 1):0]}) : ({iota_data[1][2][3][(W - 1):(W / 2)], state_in[1][2][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][2][4][(W - 1):(W / 2)], iota_data[1][2][4][((W / 2) - 1):0]}) : ({iota_data[1][2][4][(W - 1):(W / 2)], state_in[1][2][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][0][(W - 1):(W / 2)], iota_data[1][3][0][((W / 2) - 1):0]}) : ({iota_data[1][3][0][(W - 1):(W / 2)], state_in[1][3][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][1][(W - 1):(W / 2)], iota_data[1][3][1][((W / 2) - 1):0]}) : ({iota_data[1][3][1][(W - 1):(W / 2)], state_in[1][3][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][2][(W - 1):(W / 2)], iota_data[1][3][2][((W / 2) - 1):0]}) : ({iota_data[1][3][2][(W - 1):(W / 2)], state_in[1][3][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][3][(W - 1):(W / 2)], iota_data[1][3][3][((W / 2) - 1):0]}) : ({iota_data[1][3][3][(W - 1):(W / 2)], state_in[1][3][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][3][4][(W - 1):(W / 2)], iota_data[1][3][4][((W / 2) - 1):0]}) : ({iota_data[1][3][4][(W - 1):(W / 2)], state_in[1][3][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][0][(W - 1):(W / 2)], iota_data[1][4][0][((W / 2) - 1):0]}) : ({iota_data[1][4][0][(W - 1):(W / 2)], state_in[1][4][0][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][1][(W - 1):(W / 2)], iota_data[1][4][1][((W / 2) - 1):0]}) : ({iota_data[1][4][1][(W - 1):(W / 2)], state_in[1][4][1][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][2][(W - 1):(W / 2)], iota_data[1][4][2][((W / 2) - 1):0]}) : ({iota_data[1][4][2][(W - 1):(W / 2)], state_in[1][4][2][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][3][(W - 1):(W / 2)], iota_data[1][4][3][((W / 2) - 1):0]}) : ({iota_data[1][4][3][(W - 1):(W / 2)], state_in[1][4][3][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION 
 Number  Term
      1  g_2share_chi.out_data_low ? ({state_in[1][4][4][(W - 1):(W / 2)], iota_data[1][4][4][((W / 2) - 1):0]}) : ({iota_data[1][4][4][(W - 1):(W / 2)], state_in[1][4][4][((W / 2) - 1):0]}))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       466
 EXPRESSION (in == 0)
            ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       492
 EXPRESSION ((z == 0) ? ((W - 1)) : ((z - 1)))
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       492
 SUB-EXPRESSION (z == 0)
                ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       493
 EXPRESSION (c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z])
             ----------1----------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
Branches		164	161	98.17
TERNARY	306	2	2	100.00
TERNARY	307	2	2	100.00
TERNARY	308	2	2	100.00
TERNARY	309	2	2	100.00
TERNARY	315	2	2	100.00
TERNARY	306	2	2	100.00
TERNARY	307	2	2	100.00
TERNARY	308	2	2	100.00
TERNARY	309	2	2	100.00
TERNARY	315	2	2	100.00
TERNARY	306	2	2	100.00
TERNARY	307	2	2	100.00
TERNARY	308	2	2	100.00
TERNARY	309	2	2	100.00
TERNARY	315	2	2	100.00
TERNARY	306	2	2	100.00
TERNARY	307	2	2	100.00
TERNARY	308	2	2	100.00
TERNARY	309	2	2	100.00
TERNARY	315	2	2	100.00
TERNARY	306	2	2	100.00
TERNARY	307	2	2	100.00
TERNARY	308	2	2	100.00
TERNARY	309	2	2	100.00
TERNARY	315	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
TERNARY	363	2	2	100.00
TERNARY	366	2	2	100.00
CASE	98	3	2	66.67
IF	175	2	2	100.00
CASE	205	5	4	80.00
IF	466	2	2	100.00
TERNARY	492	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	306	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	307	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	308	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	309	(g_2share_chi.in_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	(g_2share_chi.in_rand_ext) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	363	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	366	(g_2share_chi.out_data_low) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	98	case (phase_sel_i)

Branches:

-1-	Status	Tests
MuBi4False	Covered	T4,T5,T6
MuBi4True	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	175	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	205	case (cycle_i)

Branches:

-1-	Status	Tests
2'h0	Covered	T4,T5,T6
2'h1	Covered	T4,T5,T6
2'h2	Covered	T4,T5,T6
2'h3	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	466	if ((in == 0))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	((z == 0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T5,T6

---

Assert Coverage for Module : keccak_2share

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidL_A	1055	1055	0	0
ValidRound_A	1055	1055	0	0
ValidW_A	1055	1055	0	0
ValidWidth_A	1055	1055	0	0
gen_selperiod_chk.SelStayTwoCycleIfTrue_A	2147483647	78514416	0	0

ValidL_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ValidRound_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ValidW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

gen_selperiod_chk.SelStayTwoCycleIfTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	78514416	0	0
T4	149799	30192	0	0
T5	205696	133008	0	0
T6	608761	132624	0	0
T10	419387	17496	0	0
T11	153221	28944	0	0
T12	1644	24	0	0
T34	627816	132624	0	0
T35	193791	132624	0	0
T36	2488	0	0	0
T37	228135	49992	0	0
T47	0	130248	0	0