Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1853223	0	0
entropy_period_rd_A	2147483647	2530	0	0
intr_enable_rd_A	2147483647	2812	0	0
prefix_0_rd_A	2147483647	2518	0	0
prefix_10_rd_A	2147483647	2280	0	0
prefix_1_rd_A	2147483647	2557	0	0
prefix_2_rd_A	2147483647	2417	0	0
prefix_3_rd_A	2147483647	2573	0	0
prefix_4_rd_A	2147483647	2504	0	0
prefix_5_rd_A	2147483647	2652	0	0
prefix_6_rd_A	2147483647	2401	0	0
prefix_7_rd_A	2147483647	2422	0	0
prefix_8_rd_A	2147483647	2385	0	0
prefix_9_rd_A	2147483647	2452	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1853223	0	0
T1	9939	1	0	0
T2	1599	0	0	0
T3	15920	0	0	0
T59	1187	0	0	0
T60	10355	0	0	0
T61	768	0	0	0
T62	2340	55	0	0
T63	11566	234	0	0
T64	1519	0	0	0
T65	19513	3	0	0
T66	0	166	0	0
T68	0	3	0	0
T118	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T125	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2530	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T71	0	2	0	0
T76	3138	7	0	0
T77	1331	0	0	0
T94	0	46	0	0
T95	0	34	0	0
T96	0	57	0	0
T99	2027	0	0	0
T118	12334	50	0	0
T121	0	140	0	0
T123	0	56	0	0
T128	0	44	0	0
T143	8731	0	0	0
T145	0	18	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2812	0	0
T59	1187	10	0	0
T60	10355	0	0	0
T61	768	0	0	0
T62	2340	0	0	0
T63	11566	0	0	0
T64	1519	10	0	0
T65	19513	0	0	0
T67	1399	0	0	0
T75	2071	0	0	0
T76	3138	3	0	0
T95	0	36	0	0
T118	0	59	0	0
T121	0	124	0	0
T123	0	97	0	0
T128	0	60	0	0
T145	0	35	0	0
T147	0	17	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2518	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T76	3138	10	0	0
T77	1331	0	0	0
T94	0	17	0	0
T95	0	31	0	0
T96	0	19	0	0
T99	2027	0	0	0
T118	12334	52	0	0
T121	0	96	0	0
T123	0	49	0	0
T128	0	60	0	0
T143	8731	0	0	0
T145	0	3	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0
T149	0	203	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2280	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T76	3138	6	0	0
T77	1331	0	0	0
T94	0	32	0	0
T95	0	31	0	0
T96	0	17	0	0
T99	2027	0	0	0
T118	12334	34	0	0
T121	0	100	0	0
T123	0	37	0	0
T128	0	45	0	0
T143	8731	0	0	0
T145	0	1	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0
T149	0	234	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2557	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T76	3138	6	0	0
T77	1331	0	0	0
T94	0	28	0	0
T95	0	24	0	0
T96	0	30	0	0
T99	2027	0	0	0
T118	12334	50	0	0
T121	0	67	0	0
T123	0	50	0	0
T128	0	49	0	0
T143	8731	0	0	0
T145	0	3	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0
T149	0	220	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2417	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T71	0	2	0	0
T76	3138	7	0	0
T77	1331	0	0	0
T94	0	13	0	0
T95	0	27	0	0
T96	0	39	0	0
T99	2027	0	0	0
T118	12334	53	0	0
T121	0	63	0	0
T123	0	34	0	0
T128	0	21	0	0
T143	8731	0	0	0
T145	0	42	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2573	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T76	3138	7	0	0
T77	1331	0	0	0
T94	0	13	0	0
T95	0	28	0	0
T96	0	37	0	0
T99	2027	0	0	0
T118	12334	48	0	0
T121	0	98	0	0
T123	0	32	0	0
T128	0	57	0	0
T143	8731	0	0	0
T145	0	17	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0
T149	0	223	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2504	0	0
T63	11566	3	0	0
T64	1519	0	0	0
T65	19513	0	0	0
T66	3627	0	0	0
T67	1399	0	0	0
T68	1486	0	0	0
T75	2071	0	0	0
T76	3138	11	0	0
T77	1331	0	0	0
T94	0	24	0	0
T95	0	27	0	0
T96	0	20	0	0
T99	2027	0	0	0
T118	0	44	0	0
T121	0	77	0	0
T123	0	39	0	0
T128	0	101	0	0
T145	0	57	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2652	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T76	3138	12	0	0
T77	1331	0	0	0
T94	0	25	0	0
T95	0	14	0	0
T96	0	31	0	0
T99	2027	0	0	0
T118	12334	33	0	0
T121	0	114	0	0
T123	0	39	0	0
T128	0	44	0	0
T143	8731	0	0	0
T145	0	3	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0
T149	0	241	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2401	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T76	3138	10	0	0
T77	1331	0	0	0
T94	0	22	0	0
T95	0	18	0	0
T96	0	15	0	0
T99	2027	0	0	0
T118	12334	36	0	0
T121	0	66	0	0
T123	0	45	0	0
T128	0	51	0	0
T143	8731	0	0	0
T145	0	14	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0
T149	0	226	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2422	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T76	3138	13	0	0
T77	1331	0	0	0
T94	0	32	0	0
T95	0	32	0	0
T96	0	27	0	0
T99	2027	0	0	0
T118	12334	47	0	0
T121	0	82	0	0
T123	0	41	0	0
T128	0	31	0	0
T143	8731	0	0	0
T145	0	36	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0
T149	0	236	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2385	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T76	3138	6	0	0
T77	1331	0	0	0
T94	0	23	0	0
T95	0	16	0	0
T96	0	23	0	0
T99	2027	0	0	0
T118	12334	33	0	0
T121	0	77	0	0
T123	0	47	0	0
T128	0	22	0	0
T143	8731	0	0	0
T145	0	35	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0
T149	0	240	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2452	0	0
T66	3627	0	0	0
T68	1486	0	0	0
T76	3138	7	0	0
T77	1331	0	0	0
T94	0	19	0	0
T95	0	15	0	0
T96	0	39	0	0
T99	2027	0	0	0
T118	12334	36	0	0
T121	0	99	0	0
T123	0	55	0	0
T128	0	39	0	0
T143	8731	0	0	0
T145	0	36	0	0
T146	1131	0	0	0
T147	931	0	0	0
T148	1023	0	0	0
T149	0	203	0	0