Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
192666 |
1 |
|
|
T4 |
760 |
|
T6 |
336 |
|
T37 |
545 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
108134 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59015 |
1 |
|
|
T4 |
748 |
|
T6 |
12 |
|
T37 |
535 |
seven_bytes |
3673 |
1 |
|
|
T6 |
9 |
|
T42 |
84 |
|
T27 |
35 |
six_bytes |
3632 |
1 |
|
|
T6 |
14 |
|
T42 |
69 |
|
T27 |
34 |
five_bytes |
3643 |
1 |
|
|
T6 |
8 |
|
T42 |
67 |
|
T27 |
26 |
four_bytes |
3665 |
1 |
|
|
T6 |
9 |
|
T42 |
75 |
|
T27 |
40 |
three_bytes |
3690 |
1 |
|
|
T6 |
10 |
|
T42 |
87 |
|
T27 |
24 |
two_bytes |
3639 |
1 |
|
|
T6 |
8 |
|
T42 |
84 |
|
T27 |
32 |
one_byte |
3575 |
1 |
|
|
T6 |
5 |
|
T42 |
81 |
|
T27 |
40 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
189182 |
1 |
|
|
T4 |
736 |
|
T6 |
330 |
|
T37 |
525 |
auto[1] |
3484 |
1 |
|
|
T4 |
24 |
|
T6 |
6 |
|
T37 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
192666 |
1 |
|
|
T4 |
760 |
|
T6 |
336 |
|
T37 |
545 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
192655 |
1 |
|
|
T4 |
760 |
|
T6 |
336 |
|
T37 |
545 |
auto[1] |
11 |
1 |
|
|
T158 |
1 |
|
T54 |
1 |
|
T159 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1145 |
1 |
|
|
T4 |
12 |
|
T6 |
1 |
|
T37 |
10 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3484 |
1 |
|
|
T4 |
24 |
|
T6 |
6 |
|
T37 |
20 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
192625 |
1 |
|
|
T4 |
588 |
|
T6 |
598 |
|
T37 |
804 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
107623 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59632 |
1 |
|
|
T4 |
578 |
|
T6 |
18 |
|
T37 |
792 |
seven_bytes |
3711 |
1 |
|
|
T6 |
17 |
|
T42 |
45 |
|
T27 |
33 |
six_bytes |
3630 |
1 |
|
|
T6 |
14 |
|
T42 |
22 |
|
T27 |
39 |
five_bytes |
3667 |
1 |
|
|
T6 |
23 |
|
T42 |
34 |
|
T27 |
52 |
four_bytes |
3596 |
1 |
|
|
T6 |
19 |
|
T42 |
33 |
|
T27 |
45 |
three_bytes |
3597 |
1 |
|
|
T6 |
17 |
|
T42 |
44 |
|
T27 |
50 |
two_bytes |
3631 |
1 |
|
|
T6 |
13 |
|
T42 |
32 |
|
T27 |
50 |
one_byte |
3538 |
1 |
|
|
T6 |
18 |
|
T42 |
26 |
|
T27 |
46 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
189129 |
1 |
|
|
T4 |
568 |
|
T6 |
590 |
|
T37 |
780 |
auto[1] |
3496 |
1 |
|
|
T4 |
20 |
|
T6 |
8 |
|
T37 |
24 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
192625 |
1 |
|
|
T4 |
588 |
|
T6 |
598 |
|
T37 |
804 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
192606 |
1 |
|
|
T4 |
587 |
|
T6 |
598 |
|
T37 |
804 |
auto[1] |
19 |
1 |
|
|
T4 |
1 |
|
T27 |
1 |
|
T18 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1165 |
1 |
|
|
T4 |
10 |
|
T6 |
1 |
|
T37 |
12 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3496 |
1 |
|
|
T4 |
20 |
|
T6 |
8 |
|
T37 |
24 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
377577 |
1 |
|
|
T4 |
837 |
|
T6 |
2352 |
|
T37 |
2002 |
auto[1] |
429 |
1 |
|
|
T52 |
27 |
|
T53 |
61 |
|
T54 |
21 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
205068 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
124189 |
1 |
|
|
T4 |
821 |
|
T6 |
59 |
|
T37 |
1964 |
seven_bytes |
7027 |
1 |
|
|
T6 |
61 |
|
T42 |
71 |
|
T27 |
97 |
six_bytes |
7052 |
1 |
|
|
T6 |
63 |
|
T42 |
61 |
|
T27 |
103 |
five_bytes |
6989 |
1 |
|
|
T6 |
76 |
|
T42 |
63 |
|
T27 |
96 |
four_bytes |
6840 |
1 |
|
|
T6 |
67 |
|
T42 |
57 |
|
T27 |
107 |
three_bytes |
7000 |
1 |
|
|
T6 |
71 |
|
T42 |
52 |
|
T27 |
90 |
two_bytes |
6935 |
1 |
|
|
T6 |
57 |
|
T42 |
61 |
|
T27 |
102 |
one_byte |
6906 |
1 |
|
|
T6 |
67 |
|
T42 |
63 |
|
T27 |
116 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
370882 |
1 |
|
|
T4 |
805 |
|
T6 |
2318 |
|
T37 |
1926 |
auto[1] |
7124 |
1 |
|
|
T4 |
32 |
|
T6 |
34 |
|
T37 |
76 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
378006 |
1 |
|
|
T4 |
837 |
|
T6 |
2352 |
|
T37 |
2002 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
377978 |
1 |
|
|
T4 |
836 |
|
T6 |
2352 |
|
T37 |
2002 |
auto[1] |
28 |
1 |
|
|
T4 |
1 |
|
T38 |
1 |
|
T40 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2393 |
1 |
|
|
T4 |
16 |
|
T6 |
9 |
|
T37 |
38 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
7124 |
1 |
|
|
T4 |
32 |
|
T6 |
34 |
|
T37 |
76 |