Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	261475566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

189837228

1

T1

10430

T2

46

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	233294165	1			T1	7221		T2	63		T3	19
values[0x0]	104589050	1			T1	3705		T2	13		T3	8
values[0x1]	113429579	1			T1	3759		T2	23		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202888104	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

248424690

1

T1

11206

T2

61

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1335639	1			T1	55		T62	30		T68	2
valid_sources[0x01]	1819320	1			T1	55		T62	46		T64	1
valid_sources[0x02]	1323730	1			T1	66		T64	2		T65	2
valid_sources[0x03]	1328551	1			T1	65		T67	1		T75	1
valid_sources[0x04]	1337112	1			T1	56		T64	3		T67	4
valid_sources[0x05]	1775960	1			T1	59		T62	68		T67	2
valid_sources[0x06]	1335320	1			T1	72		T67	2		T78	5
valid_sources[0x07]	2226552	1			T1	57		T67	3		T78	7
valid_sources[0x08]	3698927	1			T1	60		T62	43		T64	3
valid_sources[0x09]	1375085	1			T1	75		T64	2		T65	4
valid_sources[0x0a]	1996786	1			T1	57		T64	3		T67	2
valid_sources[0x0b]	1326718	1			T1	73		T62	15		T65	6
valid_sources[0x0c]	2247342	1			T1	30		T62	31		T65	2
valid_sources[0x0d]	1330423	1			T1	73		T62	14		T64	2
valid_sources[0x0e]	3296229	1			T1	67		T64	1		T68	4
valid_sources[0x0f]	1329097	1			T1	55		T67	2		T68	1
valid_sources[0x10]	1336692	1			T1	66		T64	2		T65	5
valid_sources[0x11]	1363631	1			T1	63		T61	56		T62	6
valid_sources[0x12]	1779414	1			T1	51		T62	68		T64	1
valid_sources[0x13]	2253229	1			T1	73		T64	7		T65	1
valid_sources[0x14]	1330496	1			T1	45		T62	11		T64	3
valid_sources[0x15]	1326866	1			T1	75		T61	62		T64	1
valid_sources[0x16]	1331073	1			T1	67		T64	4		T78	8
valid_sources[0x17]	2188877	1			T1	71		T61	208		T75	1
valid_sources[0x18]	3678060	1			T1	86		T62	2		T64	1
valid_sources[0x19]	2176104	1			T1	54		T64	1		T67	1
valid_sources[0x1a]	1328142	1			T1	66		T64	2		T68	3
valid_sources[0x1b]	1330497	1			T1	61		T64	1		T78	4
valid_sources[0x1c]	1534269	1			T1	77		T62	12		T64	3
valid_sources[0x1d]	1332014	1			T1	73		T64	1		T67	1
valid_sources[0x1e]	1328573	1			T1	57		T78	1		T79	17
valid_sources[0x1f]	1569446	1			T1	37		T62	6		T68	2
valid_sources[0x20]	1323067	1			T1	34		T64	1		T65	3
valid_sources[0x21]	2988351	1			T1	77		T67	3		T78	3
valid_sources[0x22]	1329706	1			T1	40		T62	12		T64	2
valid_sources[0x23]	1320616	1			T1	65		T64	2		T78	4
valid_sources[0x24]	3249849	1			T1	36		T64	1		T67	3
valid_sources[0x25]	1326626	1			T1	68		T62	65		T64	3
valid_sources[0x26]	1324345	1			T1	73		T65	1		T67	1
valid_sources[0x27]	1318819	1			T1	74		T65	6		T67	1
valid_sources[0x28]	1330141	1			T1	60		T65	2		T70	1
valid_sources[0x29]	1326475	1			T1	55		T64	1		T67	2
valid_sources[0x2a]	4314741	1			T1	59		T65	4		T67	3
valid_sources[0x2b]	1961552	1			T1	52		T2	49		T75	1
valid_sources[0x2c]	1375869	1			T1	52		T64	2		T68	2
valid_sources[0x2d]	1353818	1			T1	57		T62	28		T64	3
valid_sources[0x2e]	1322450	1			T1	68		T64	1		T65	11
valid_sources[0x2f]	1352467	1			T1	80		T64	2		T65	6
valid_sources[0x30]	1323352	1			T1	69		T67	1		T78	2
valid_sources[0x31]	1327191	1			T1	58		T78	5		T79	7
valid_sources[0x32]	1324943	1			T1	67		T64	2		T78	13
valid_sources[0x33]	4642085	1			T1	62		T64	2		T79	5
valid_sources[0x34]	1328694	1			T1	48		T64	2		T67	1
valid_sources[0x35]	1782202	1			T1	44		T67	2		T78	4
valid_sources[0x36]	1324573	1			T1	44		T64	8		T65	6
valid_sources[0x37]	1327361	1			T1	68		T67	1		T68	2
valid_sources[0x38]	1335187	1			T1	30		T67	1		T68	1
valid_sources[0x39]	1344222	1			T1	63		T64	8		T79	6
valid_sources[0x3a]	1455624	1			T1	49		T67	1		T68	3
valid_sources[0x3b]	1496753	1			T1	64		T64	1		T65	5
valid_sources[0x3c]	1345528	1			T1	55		T68	1		T78	8
valid_sources[0x3d]	1344727	1			T1	38		T62	8		T67	1
valid_sources[0x3e]	1414679	1			T1	61		T64	1		T75	3
valid_sources[0x3f]	1320827	1			T1	51		T62	40		T67	3
valid_sources[0x40]	1969437	1			T1	72		T62	43		T64	1
valid_sources[0x41]	2360865	1			T1	57		T67	1		T78	3
valid_sources[0x42]	1447219	1			T1	57		T62	12		T64	1
valid_sources[0x43]	1328893	1			T1	60		T64	1		T68	2
valid_sources[0x44]	1328934	1			T1	76		T64	1		T67	2
valid_sources[0x45]	4148856	1			T1	71		T64	3		T75	1
valid_sources[0x46]	1331144	1			T1	62		T64	2		T69	1
valid_sources[0x47]	1433170	1			T1	46		T64	1		T67	3
valid_sources[0x48]	1332264	1			T1	53		T62	7		T64	3
valid_sources[0x49]	1345299	1			T1	59		T64	1		T65	1
valid_sources[0x4a]	2380664	1			T1	43		T62	59		T68	2
valid_sources[0x4b]	1575447	1			T1	52		T68	3		T78	2
valid_sources[0x4c]	3668098	1			T1	53		T67	1		T68	1
valid_sources[0x4d]	1332105	1			T1	67		T62	115		T75	1
valid_sources[0x4e]	1320128	1			T1	44		T62	80		T64	1
valid_sources[0x4f]	3678554	1			T1	90		T64	3		T67	4
valid_sources[0x50]	1323777	1			T1	56		T62	77		T64	1
valid_sources[0x51]	1339118	1			T1	52		T67	1		T68	1
valid_sources[0x52]	1330983	1			T1	65		T64	1		T65	1
valid_sources[0x53]	1475850	1			T1	69		T62	1		T76	55
valid_sources[0x54]	1322916	1			T1	48		T67	1		T68	1
valid_sources[0x55]	2020281	1			T1	58		T67	1		T68	4
valid_sources[0x56]	2248254	1			T1	70		T62	36		T64	2
valid_sources[0x57]	1375205	1			T1	63		T62	79		T67	1
valid_sources[0x58]	1323833	1			T1	34		T62	5		T65	2
valid_sources[0x59]	1996634	1			T1	72		T2	16		T64	2
valid_sources[0x5a]	1625374	1			T1	51		T68	2		T78	9
valid_sources[0x5b]	1494812	1			T1	60		T61	54		T64	1
valid_sources[0x5c]	1332750	1			T1	47		T64	3		T67	3
valid_sources[0x5d]	2178182	1			T1	57		T62	5		T67	1
valid_sources[0x5e]	1332372	1			T1	64		T68	1		T79	19
valid_sources[0x5f]	1330901	1			T1	50		T62	22		T64	4
valid_sources[0x60]	3689536	1			T1	73		T62	43		T64	2
valid_sources[0x61]	1438800	1			T1	50		T64	1		T68	2
valid_sources[0x62]	1325984	1			T1	52		T68	1		T78	2
valid_sources[0x63]	1508535	1			T1	61		T65	1		T68	3
valid_sources[0x64]	1320023	1			T1	37		T62	44		T65	4
valid_sources[0x65]	1329935	1			T1	40		T62	38		T79	12
valid_sources[0x66]	2355509	1			T1	45		T62	26		T68	2
valid_sources[0x67]	1365439	1			T1	39		T64	3		T65	2
valid_sources[0x68]	2217106	1			T1	77		T64	3		T67	1
valid_sources[0x69]	1371917	1			T1	39		T62	18		T64	1
valid_sources[0x6a]	3650320	1			T1	60		T64	2		T65	4
valid_sources[0x6b]	3642552	1			T1	49		T67	2		T68	1
valid_sources[0x6c]	1381130	1			T1	55		T62	9		T67	1
valid_sources[0x6d]	2231737	1			T1	72		T65	1		T67	3
valid_sources[0x6e]	1325262	1			T1	79		T62	85		T64	3
valid_sources[0x6f]	1332364	1			T1	53		T64	1		T67	1
valid_sources[0x70]	1330198	1			T1	67		T64	1		T65	1
valid_sources[0x71]	1340149	1			T1	46		T62	7		T65	1
valid_sources[0x72]	1326043	1			T1	40		T78	2		T79	8
valid_sources[0x73]	1325176	1			T1	40		T68	5		T78	2
valid_sources[0x74]	1531175	1			T1	52		T64	5		T68	2
valid_sources[0x75]	1330976	1			T1	71		T67	1		T68	2
valid_sources[0x76]	3654067	1			T1	58		T64	2		T67	1
valid_sources[0x77]	1319702	1			T1	56		T62	41		T67	3
valid_sources[0x78]	1369238	1			T1	59		T65	1		T67	1
valid_sources[0x79]	1329020	1			T1	46		T62	70		T64	1
valid_sources[0x7a]	1352035	1			T1	43		T2	15		T62	39
valid_sources[0x7b]	1336875	1			T1	51		T64	1		T67	1
valid_sources[0x7c]	1991146	1			T1	68		T67	1		T68	1
valid_sources[0x7d]	1420122	1			T1	53		T62	8		T64	1
valid_sources[0x7e]	1353064	1			T1	63		T64	1		T66	66
valid_sources[0x7f]	1330955	1			T1	84		T67	1		T75	2
valid_sources[0x80]	1534255	1			T1	38		T64	2		T65	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73279785

1

T1

3538

T2

27

T3

8

values[0x0]

all_enables

biggest_size

62503813

1

T1

3468

T2

7

T3

1

values[0x1]

all_enables

biggest_size

54053630

1

T1

3424

T2

12

T3

2