Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

270862464

1

T1

4255

T2

53

T3

27

full_word

190416194

1

T1

10430

T2

46

T3

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	461278308	1			T1	14685		T2	99		T3	38
auto[TlIntgErrCmd]	114	1			T62	6		T79	5		T125	11
auto[TlIntgErrData]	117	1			T62	4		T79	5		T125	6
auto[TlIntgErrBoth]	119	1			T62	10		T79	10		T125	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235084151

1

T1

7221

T2

63

T3

19

auto[1]

226194507

1

T1

7464

T2

36

T3

19

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161659027	1			T1	3683		T2	36		T3	11
auto[TlIntgErrNone]	partial	auto[1]	109203125	1			T1	572		T2	17		T3	16
auto[TlIntgErrNone]	full_word	auto[0]	73424968	1			T1	3538		T2	27		T3	8
auto[TlIntgErrNone]	full_word	auto[1]	116991188	1			T1	6892		T2	19		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T62	1		T79	3		T125	4
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T62	3		T79	2		T125	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T62	1		T164	1		T165	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T62	1		T129	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T79	4		T125	2		T126	5
auto[TlIntgErrData]	partial	auto[1]	50	1			T62	4		T79	1		T125	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T129	1		T130	1		T165	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T125	1		T128	3		T166	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T62	5		T79	1		T125	3
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T62	5		T79	9		T128	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T128	1		T164	1		T149	2
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T128	1		T126	1		T164	1