Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	348304	0	0
RunThenComplete_M	2147483647	3118442	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348304	0	0
T4	884963	109	0	0
T5	386719	176	0	0
T6	271688	55	0	0
T10	391902	134	0	0
T11	3079	0	0	0
T12	3141	0	0	0
T32	641204	390	0	0
T33	176134	2337	0	0
T34	172728	2337	0	0
T35	669296	390	0	0
T36	0	39	0	0
T37	0	174	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3118442	0	0
T4	884963	532	0	0
T5	386719	444	0	0
T6	271688	259	0	0
T10	391902	713	0	0
T11	3079	0	0	0
T12	3141	0	0	0
T32	641204	5542	0	0
T33	176134	13147	0	0
T34	172728	13147	0	0
T35	669296	5542	0	0
T36	0	1549	0	0
T37	0	857	0	0