Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2107549	0	0
entropy_period_rd_A	2147483647	3216	0	0
intr_enable_rd_A	2147483647	3478	0	0
prefix_0_rd_A	2147483647	3094	0	0
prefix_10_rd_A	2147483647	2747	0	0
prefix_1_rd_A	2147483647	2957	0	0
prefix_2_rd_A	2147483647	2935	0	0
prefix_3_rd_A	2147483647	2964	0	0
prefix_4_rd_A	2147483647	2983	0	0
prefix_5_rd_A	2147483647	2988	0	0
prefix_6_rd_A	2147483647	2879	0	0
prefix_7_rd_A	2147483647	3054	0	0
prefix_8_rd_A	2147483647	2996	0	0
prefix_9_rd_A	2147483647	3247	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2107549	0	0
T2	1692	1	0	0
T3	879	0	0	0
T61	6486	0	0	0
T62	28153	4	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	0	0	0
T66	1579	0	0	0
T67	6545	53	0	0
T68	0	152	0	0
T69	1371	0	0	0
T71	0	212	0	0
T79	0	3	0	0
T80	0	1	0	0
T125	0	1	0	0
T126	0	2	0	0
T128	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3216	0	0
T1	154332	217	0	0
T2	1692	1	0	0
T3	879	0	0	0
T61	6486	21	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	24	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	1	0	0
T99	0	5	0	0
T103	0	9	0	0
T104	0	27	0	0
T125	0	107	0	0
T126	0	129	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3478	0	0
T1	154332	421	0	0
T2	1692	0	0	0
T3	879	0	0	0
T61	6486	51	0	0
T62	28153	0	0	0
T63	1611	29	0	0
T64	2324	0	0	0
T65	2990	15	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	4	0	0
T99	0	12	0	0
T104	0	49	0	0
T125	0	155	0	0
T126	0	125	0	0
T155	0	17	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3094	0	0
T1	154332	466	0	0
T2	1692	7	0	0
T3	879	0	0	0
T61	6486	31	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	4	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	13	0	0
T95	0	31	0	0
T99	0	7	0	0
T104	0	23	0	0
T125	0	82	0	0
T126	0	76	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2747	0	0
T1	154332	404	0	0
T2	1692	0	0	0
T3	879	0	0	0
T61	6486	20	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	5	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	3	0	0
T95	0	25	0	0
T99	0	9	0	0
T103	0	10	0	0
T104	0	26	0	0
T125	0	75	0	0
T126	0	80	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2957	0	0
T1	154332	420	0	0
T2	1692	6	0	0
T3	879	0	0	0
T61	6486	15	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	6	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	7	0	0
T99	0	1	0	0
T103	0	3	0	0
T104	0	14	0	0
T125	0	93	0	0
T126	0	79	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2935	0	0
T1	154332	446	0	0
T2	1692	4	0	0
T3	879	0	0	0
T61	6486	35	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	5	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	9	0	0
T99	0	8	0	0
T103	0	4	0	0
T104	0	30	0	0
T125	0	66	0	0
T126	0	84	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2964	0	0
T1	154332	459	0	0
T2	1692	2	0	0
T3	879	0	0	0
T61	6486	4	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	16	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	17	0	0
T95	0	22	0	0
T103	0	6	0	0
T104	0	20	0	0
T125	0	61	0	0
T126	0	99	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2983	0	0
T1	154332	487	0	0
T2	1692	5	0	0
T3	879	0	0	0
T61	6486	9	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	7	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	6	0	0
T99	0	12	0	0
T103	0	5	0	0
T104	0	29	0	0
T125	0	89	0	0
T126	0	83	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2988	0	0
T1	154332	501	0	0
T2	1692	1	0	0
T3	879	0	0	0
T61	6486	16	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	16	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	8	0	0
T95	0	16	0	0
T99	0	7	0	0
T104	0	23	0	0
T125	0	68	0	0
T126	0	92	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2879	0	0
T1	154332	418	0	0
T2	1692	8	0	0
T3	879	0	0	0
T61	6486	21	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	6	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	11	0	0
T99	0	8	0	0
T103	0	1	0	0
T104	0	23	0	0
T125	0	84	0	0
T126	0	94	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3054	0	0
T1	154332	453	0	0
T2	1692	6	0	0
T3	879	0	0	0
T61	6486	11	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	2	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	4	0	0
T95	0	17	0	0
T99	0	7	0	0
T104	0	28	0	0
T125	0	80	0	0
T126	0	81	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2996	0	0
T1	154332	452	0	0
T2	1692	4	0	0
T3	879	0	0	0
T61	6486	21	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	11	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	6	0	0
T99	0	14	0	0
T103	0	1	0	0
T104	0	34	0	0
T125	0	80	0	0
T126	0	73	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3247	0	0
T1	154332	473	0	0
T2	1692	4	0	0
T3	879	0	0	0
T61	6486	25	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	10	0	0
T66	1579	0	0	0
T67	6545	0	0	0
T70	0	14	0	0
T99	0	6	0	0
T103	0	8	0	0
T104	0	10	0	0
T125	0	57	0	0
T126	0	79	0	0