Unified Coverage Report :: Group :: kmac_env_pkg::app_cg_wrap::app_cg

Group : kmac_env_pkg::app_cg_wrap::app_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
94.44	90.74	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
AppLc_cg	88.89	1	100	1	64	64
AppRom_cg	88.89	1	100	1	64	64
AppKeymgr_cg	94.44	1	100	1	64	64

---

Group Instance : AppLc_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance AppLc_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	2	14	87.50
Crosses	2	0	2	100.00

Variables for Group Instance AppLc_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
app_err	2	1	1	50.00	100	1	1	2
data_strb	8	0	8	100.00	100	1	1	0
done	2	0	2	100.00	100	1	1	2
in_keccak_rounds	2	1	1	50.00	100	1	1	2
single_data_beat	2	0	2	100.00	100	1	1	2

Crosses for Group Instance AppLc_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
partial_data_on_last_beat	1	0	1	100.00	100	1	1	0
done_in_keccak_rounds	1	0	1	100.00	100	1	1	0

---

Group Instance : AppRom_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance AppRom_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	2	14	87.50
Crosses	2	0	2	100.00

Variables for Group Instance AppRom_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
app_err	2	1	1	50.00	100	1	1	2
data_strb	8	0	8	100.00	100	1	1	0
done	2	0	2	100.00	100	1	1	2
in_keccak_rounds	2	1	1	50.00	100	1	1	2
single_data_beat	2	0	2	100.00	100	1	1	2

Crosses for Group Instance AppRom_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
partial_data_on_last_beat	1	0	1	100.00	100	1	1	0
done_in_keccak_rounds	1	0	1	100.00	100	1	1	0

---

Group Instance : AppKeymgr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

---

Summary for Group Instance AppKeymgr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	1	15	93.75
Crosses	2	0	2	100.00

Variables for Group Instance AppKeymgr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
app_err	2	0	2	100.00	100	1	1	2
data_strb	8	0	8	100.00	100	1	1	0
done	2	0	2	100.00	100	1	1	2
in_keccak_rounds	2	1	1	50.00	100	1	1	2
single_data_beat	2	0	2	100.00	100	1	1	2

Crosses for Group Instance AppKeymgr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
partial_data_on_last_beat	1	0	1	100.00	100	1	1	0
done_in_keccak_rounds	1	0	1	100.00	100	1	1	0

Summary for Variable app_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for app_err

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173014

1

T4

343

T6

1845

T32

3648

---

Summary for Variable data_strb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for data_strb

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	84480	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full_data_beat	68568	1			T4	336		T6	54		T32	3598
seven_bytes	2857	1			T6	54		T10	61		T35	14
six_bytes	2980	1			T6	53		T10	53		T35	11
five_bytes	2756	1			T6	41		T10	52		T35	11
four_bytes	2893	1			T6	56		T10	61		T35	11
three_bytes	2853	1			T6	49		T10	42		T35	7
two_bytes	2759	1			T6	34		T10	53		T35	7
one_byte	2868	1			T6	64		T10	45		T35	8

---

Summary for Variable done

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for done

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169586

1

T4

329

T6

1823

T32

3548

auto[1]

3428

1

T4

14

T6

22

T32

100

---

Summary for Variable in_keccak_rounds

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for in_keccak_rounds

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173014

1

T4

343

T6

1845

T32

3648

---

Summary for Variable single_data_beat

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for single_data_beat

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173002

1

T4

343

T6

1845

T32

3647

auto[1]

12

1

T32

1

T38

1

T24

1

---

Summary for Cross partial_data_on_last_beat

Samples crossed: done data_strb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for partial_data_on_last_beat

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

1214

1

T4

7

T6

2

T32

50

---

Summary for Cross done_in_keccak_rounds

Samples crossed: done in_keccak_rounds

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for done_in_keccak_rounds

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

3428

1

T4

14

T6

22

T32

100

Summary for Variable app_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for app_err

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179489

1

T4

633

T6

1270

T32

3042

---

Summary for Variable data_strb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for data_strb

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	87350	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full_data_beat	71181	1			T4	625		T6	35		T32	2996
seven_bytes	2855	1			T6	39		T10	41		T13	9
six_bytes	2957	1			T6	41		T10	53		T35	2
five_bytes	3005	1			T6	36		T10	45		T35	1
four_bytes	3034	1			T6	35		T10	36		T35	4
three_bytes	2970	1			T6	35		T10	37		T35	4
two_bytes	3049	1			T6	32		T10	45		T35	3
one_byte	3088	1			T6	52		T10	48		T35	4

---

Summary for Variable done

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for done

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175973

1

T4

617

T6

1256

T32

2950

auto[1]

3516

1

T4

16

T6

14

T32

92

---

Summary for Variable in_keccak_rounds

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for in_keccak_rounds

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179489

1

T4

633

T6

1270

T32

3042

---

Summary for Variable single_data_beat

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for single_data_beat

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179473

1

T4

633

T6

1270

T32

3040

auto[1]

16

1

T32

2

T95

1

T72

1

---

Summary for Cross partial_data_on_last_beat

Samples crossed: done data_strb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for partial_data_on_last_beat

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

1259

1

T4

8

T6

2

T32

46

---

Summary for Cross done_in_keccak_rounds

Samples crossed: done in_keccak_rounds

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for done_in_keccak_rounds

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

3516

1

T4

16

T6

14

T32

92

Summary for Variable app_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for app_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

336662

1

T4

842

T6

2587

T32

6160

auto[1]

525

1

T32

93

T49

100

T50

90

---

Summary for Variable data_strb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for data_strb

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	166032	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full_data_beat	131998	1			T4	826		T6	64		T32	6160
seven_bytes	5607	1			T6	66		T10	99		T35	20
six_bytes	5457	1			T6	78		T10	89		T35	25
five_bytes	5801	1			T6	73		T10	100		T35	21
four_bytes	5434	1			T6	52		T10	103		T35	24
three_bytes	5674	1			T6	81		T10	98		T35	20
two_bytes	5610	1			T6	73		T10	93		T35	19
one_byte	5574	1			T6	67		T10	99		T35	20

---

Summary for Variable done

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for done

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

330410

1

T4

810

T6

2551

T32

6067

auto[1]

6777

1

T4

32

T6

36

T32

186

---

Summary for Variable in_keccak_rounds

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for in_keccak_rounds

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

337187

1

T4

842

T6

2587

T32

6253

---

Summary for Variable single_data_beat

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for single_data_beat

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

337164

1

T4

842

T6

2587

T32

6251

auto[1]

23

1

T32

2

T49

1

T18

1

---

Summary for Cross partial_data_on_last_beat

Samples crossed: done data_strb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for partial_data_on_last_beat

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

2429

1

T4

16

T6

6

T32

93

---

Summary for Cross done_in_keccak_rounds

Samples crossed: done in_keccak_rounds

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for done_in_keccak_rounds

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

6777

1

T4

32

T6

36

T32

186