Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258409167

1

T1

4148

T2

820

T3

1

full_word

181687036

1

T1

10537

T2

1901

T3

658

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	440095873	1			T1	14685		T2	2701		T3	659
auto[TlIntgErrCmd]	124	1			T2	8		T58	7		T59	9
auto[TlIntgErrData]	96	1			T2	8		T58	4		T59	5
auto[TlIntgErrBoth]	110	1			T2	4		T58	9		T59	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225314586

1

T1

7221

T2

1514

T3

321

auto[1]

214781617

1

T1

7464

T2

1207

T3

338

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154930851	1			T1	3615		T2	730		T3	1
auto[TlIntgErrNone]	partial	auto[1]	103478008	1			T1	533		T2	72		T54	22
auto[TlIntgErrNone]	full_word	auto[0]	70383601	1			T1	3606		T2	771		T3	320
auto[TlIntgErrNone]	full_word	auto[1]	111303413	1			T1	6931		T2	1128		T3	338
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T2	4		T58	3		T59	3
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T2	2		T58	3		T59	6
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T2	2		T58	1		T150	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T152	1		T147	1		T148	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T2	6		T58	2		T146	4
auto[TlIntgErrData]	partial	auto[1]	51	1			T2	2		T58	2		T59	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T153	1		T154	2		T148	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T152	1		T154	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T2	1		T58	3		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T2	3		T58	5		T59	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T153	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T58	1		T147	1		T155	1