Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	111767943	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1231	1231	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111767943	0	0
T4	0	9428	0	0
T5	0	108925	0	0
T6	0	9905	0	0
T10	0	16266	0	0
T56	2238	148	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T61	0	390	0	0
T62	2367	0	0	0
T63	0	414	0	0
T64	0	56	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	0	0	0
T69	0	465	0	0
T70	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1231	1231	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	215050693	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1231	1231	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	215050693	0	0
T4	0	9428	0	0
T5	0	335999	0	0
T6	0	9905	0	0
T10	0	76607	0	0
T56	2238	255	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T61	0	195	0	0
T62	2367	0	0	0
T63	0	333	0	0
T64	0	98	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	0	0	0
T69	0	233	0	0
T70	0	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1231	1231	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	312267079	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1231	1231	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	312267079	0	0
T1	103818	14694	0	0
T2	9607	5283	0	0
T3	4953	708	0	0
T54	4488	2757	0	0
T55	779	1	0	0
T56	2238	333	0	0
T57	1236	40	0	0
T58	8612	5216	0	0
T59	10498	5260	0	0
T60	1790	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1231	1231	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	611316983	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1231	1231	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	611316983	0	0
T1	103818	14685	0	0
T2	9607	2721	0	0
T3	4953	659	0	0
T54	4488	1378	0	0
T55	779	7	0	0
T56	2238	693	0	0
T57	1236	40	0	0
T58	8612	2658	0	0
T59	10498	2696	0	0
T60	1790	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	103818	103766	0	0
T2	9607	8036	0	0
T3	4953	4876	0	0
T54	4488	4175	0	0
T55	779	702	0	0
T56	2238	2132	0	0
T57	1236	1177	0	0
T58	8612	7051	0	0
T59	10498	8890	0	0
T60	1790	1549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1231	1231	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0