Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1634063	0	0
entropy_period_rd_A	2147483647	3210	0	0
intr_enable_rd_A	2147483647	3687	0	0
prefix_0_rd_A	2147483647	2908	0	0
prefix_10_rd_A	2147483647	2846	0	0
prefix_1_rd_A	2147483647	3281	0	0
prefix_2_rd_A	2147483647	2761	0	0
prefix_3_rd_A	2147483647	3021	0	0
prefix_4_rd_A	2147483647	3076	0	0
prefix_5_rd_A	2147483647	3249	0	0
prefix_6_rd_A	2147483647	3013	0	0
prefix_7_rd_A	2147483647	3217	0	0
prefix_8_rd_A	2147483647	3115	0	0
prefix_9_rd_A	2147483647	3262	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1634063	0	0
T2	9607	1	0	0
T3	4953	0	0	0
T13	0	75386	0	0
T19	0	61417	0	0
T21	0	71995	0	0
T54	4488	0	0	0
T55	779	0	0	0
T56	2238	1	0	0
T57	1236	0	0	0
T58	8612	2	0	0
T59	10498	1	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T63	0	193	0	0
T64	0	2	0	0
T71	0	43993	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3210	0	0
T13	0	226	0	0
T21	0	79	0	0
T56	2238	14	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	9	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	26	0	0
T117	0	172	0	0
T119	0	151	0	0
T133	0	13	0	0
T134	0	191	0	0
T135	0	74	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3687	0	0
T13	0	216	0	0
T21	0	91	0	0
T56	2238	13	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	3	0	0
T65	2926	0	0	0
T66	907	14	0	0
T67	5712	0	0	0
T68	10022	19	0	0
T117	0	142	0	0
T119	0	110	0	0
T133	0	5	0	0
T136	0	4	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2908	0	0
T13	0	208	0	0
T21	0	38	0	0
T56	2238	3	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	22	0	0
T117	0	133	0	0
T119	0	83	0	0
T133	0	8	0	0
T134	0	173	0	0
T135	0	48	0	0
T137	0	236	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2846	0	0
T13	0	152	0	0
T21	0	46	0	0
T56	2238	10	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	11	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	6	0	0
T117	0	135	0	0
T119	0	110	0	0
T133	0	11	0	0
T134	0	139	0	0
T135	0	35	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3281	0	0
T13	0	231	0	0
T21	0	76	0	0
T56	2238	4	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	1	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	5	0	0
T117	0	139	0	0
T119	0	191	0	0
T133	0	10	0	0
T134	0	111	0	0
T135	0	47	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2761	0	0
T13	0	162	0	0
T21	0	80	0	0
T56	2238	12	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	1	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	8	0	0
T117	0	138	0	0
T119	0	99	0	0
T133	0	6	0	0
T134	0	148	0	0
T135	0	17	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3021	0	0
T13	0	195	0	0
T21	0	67	0	0
T56	2238	14	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	4	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	28	0	0
T117	0	159	0	0
T119	0	132	0	0
T133	0	6	0	0
T134	0	132	0	0
T135	0	45	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3076	0	0
T13	0	196	0	0
T21	0	91	0	0
T56	2238	13	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	3	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	26	0	0
T117	0	123	0	0
T119	0	131	0	0
T133	0	6	0	0
T134	0	212	0	0
T135	0	40	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3249	0	0
T13	0	250	0	0
T21	0	100	0	0
T56	2238	11	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	1	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	6	0	0
T117	0	133	0	0
T119	0	134	0	0
T133	0	8	0	0
T134	0	179	0	0
T135	0	50	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3013	0	0
T13	0	207	0	0
T21	0	119	0	0
T56	2238	3	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	2	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	19	0	0
T117	0	119	0	0
T119	0	110	0	0
T133	0	1	0	0
T134	0	142	0	0
T135	0	45	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3217	0	0
T13	0	250	0	0
T21	0	89	0	0
T56	2238	9	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T64	0	1	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	20	0	0
T117	0	157	0	0
T119	0	120	0	0
T133	0	13	0	0
T134	0	164	0	0
T135	0	53	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3115	0	0
T13	0	207	0	0
T21	0	88	0	0
T56	2238	9	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	14	0	0
T117	0	133	0	0
T119	0	149	0	0
T133	0	5	0	0
T134	0	166	0	0
T135	0	57	0	0
T137	0	238	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3262	0	0
T13	0	174	0	0
T21	0	90	0	0
T56	2238	6	0	0
T57	1236	0	0	0
T58	8612	0	0	0
T59	10498	0	0	0
T60	1790	0	0	0
T62	2367	0	0	0
T65	2926	0	0	0
T66	907	0	0	0
T67	5712	0	0	0
T68	10022	12	0	0
T117	0	142	0	0
T119	0	102	0	0
T133	0	7	0	0
T134	0	211	0	0
T135	0	39	0	0
T137	0	288	0	0