Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	262194701	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

190005584

1

T1

93

T2

71

T3

1057

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	233998811	1			T1	70		T2	143		T3	882
values[0x0]	104752531	1			T1	34		T2	3		T3	274
values[0x1]	113448943	1			T1	26		T2	7		T3	272

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203600611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

248599674

1

T1

106

T2

87

T3

1152

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1339235	1			T3	4		T47	1		T50	30
valid_sources[0x01]	1312207	1			T1	1		T3	4		T50	28
valid_sources[0x02]	1322211	1			T1	1		T2	83		T3	5
valid_sources[0x03]	1466712	1			T3	5		T50	22		T52	6
valid_sources[0x04]	1334672	1			T1	1		T3	6		T50	28
valid_sources[0x05]	1775952	1			T3	8		T50	30		T52	6
valid_sources[0x06]	1460794	1			T3	7		T50	32		T52	3
valid_sources[0x07]	2343163	1			T3	8		T50	32		T52	4
valid_sources[0x08]	3712851	1			T1	3		T3	9		T50	26
valid_sources[0x09]	1321730	1			T1	1		T3	5		T47	3
valid_sources[0x0a]	2351270	1			T1	1		T3	5		T50	21
valid_sources[0x0b]	3653030	1			T1	1		T3	1		T50	27
valid_sources[0x0c]	1325373	1			T3	8		T49	39		T50	27
valid_sources[0x0d]	1320534	1			T1	2		T3	4		T50	27
valid_sources[0x0e]	1371446	1			T3	8		T50	21		T52	2
valid_sources[0x0f]	3295681	1			T1	3		T3	5		T50	29
valid_sources[0x10]	1328380	1			T1	1		T3	5		T50	27
valid_sources[0x11]	1962436	1			T1	1		T3	7		T50	23
valid_sources[0x12]	1326360	1			T1	1		T3	4		T48	2
valid_sources[0x13]	1338246	1			T3	3		T50	29		T52	2
valid_sources[0x14]	1319871	1			T1	1		T3	3		T48	9
valid_sources[0x15]	1316804	1			T3	2		T50	25		T52	4
valid_sources[0x16]	1315386	1			T3	10		T50	32		T51	2
valid_sources[0x17]	1781084	1			T3	5		T50	21		T52	4
valid_sources[0x18]	1822954	1			T3	5		T50	26		T52	8
valid_sources[0x19]	1324019	1			T3	2		T47	1		T49	8
valid_sources[0x1a]	1315627	1			T50	26		T52	6		T54	2
valid_sources[0x1b]	1454008	1			T1	1		T3	3		T50	38
valid_sources[0x1c]	1312954	1			T3	9		T50	25		T51	1
valid_sources[0x1d]	1312021	1			T3	5		T47	2		T50	18
valid_sources[0x1e]	1487284	1			T1	1		T3	5		T47	1
valid_sources[0x1f]	3306141	1			T3	3		T50	29		T52	4
valid_sources[0x20]	1470597	1			T3	4		T50	24		T52	7
valid_sources[0x21]	1977052	1			T1	2		T3	8		T50	16
valid_sources[0x22]	1324282	1			T3	5		T50	37		T52	10
valid_sources[0x23]	1323372	1			T3	5		T50	27		T52	8
valid_sources[0x24]	1324055	1			T3	5		T50	29		T52	2
valid_sources[0x25]	1322527	1			T3	5		T50	19		T52	8
valid_sources[0x26]	1494847	1			T1	2		T3	6		T50	32
valid_sources[0x27]	2208897	1			T3	9		T50	27		T52	4
valid_sources[0x28]	1531337	1			T3	7		T50	31		T52	7
valid_sources[0x29]	3281780	1			T3	4		T48	39		T50	31
valid_sources[0x2a]	1315914	1			T1	1		T3	2		T50	22
valid_sources[0x2b]	1514157	1			T1	1		T3	6		T50	32
valid_sources[0x2c]	1319980	1			T1	1		T3	7		T50	16
valid_sources[0x2d]	1325945	1			T3	9		T47	2		T50	28
valid_sources[0x2e]	1310388	1			T1	3		T3	9		T50	27
valid_sources[0x2f]	1320326	1			T3	6		T50	28		T52	8
valid_sources[0x30]	3665787	1			T1	1		T3	6		T50	28
valid_sources[0x31]	1968915	1			T3	5		T49	23		T50	29
valid_sources[0x32]	1483215	1			T1	1		T3	5		T48	52
valid_sources[0x33]	1312641	1			T1	1		T3	6		T50	26
valid_sources[0x34]	2177949	1			T1	3		T3	1		T49	12
valid_sources[0x35]	1350263	1			T3	4		T50	30		T52	1
valid_sources[0x36]	1327202	1			T1	1		T3	7		T50	23
valid_sources[0x37]	1650977	1			T3	2		T47	2		T50	26
valid_sources[0x38]	1389123	1			T1	2		T3	9		T50	31
valid_sources[0x39]	1326599	1			T3	7		T50	43		T52	5
valid_sources[0x3a]	1321651	1			T3	5		T50	29		T52	1
valid_sources[0x3b]	1339907	1			T3	7		T50	31		T55	1
valid_sources[0x3c]	1315182	1			T3	7		T47	2		T50	14
valid_sources[0x3d]	1336974	1			T3	5		T50	22		T52	7
valid_sources[0x3e]	1479611	1			T3	8		T50	29		T52	7
valid_sources[0x3f]	2236840	1			T3	10		T50	27		T52	5
valid_sources[0x40]	1612213	1			T3	7		T50	28		T52	3
valid_sources[0x41]	1315631	1			T3	6		T49	22		T50	25
valid_sources[0x42]	1768734	1			T1	2		T3	8		T50	21
valid_sources[0x43]	1354230	1			T1	2		T3	6		T50	28
valid_sources[0x44]	3287547	1			T3	10		T50	24		T52	4
valid_sources[0x45]	1319477	1			T1	1		T3	4		T50	22
valid_sources[0x46]	1317762	1			T1	1		T3	5		T50	33
valid_sources[0x47]	1321322	1			T1	2		T3	5		T50	31
valid_sources[0x48]	1318993	1			T1	1		T3	5		T50	31
valid_sources[0x49]	1324811	1			T3	11		T49	13		T50	25
valid_sources[0x4a]	1357098	1			T3	5		T50	40		T52	3
valid_sources[0x4b]	1333257	1			T3	4		T49	18		T50	23
valid_sources[0x4c]	3286121	1			T3	5		T50	15		T52	6
valid_sources[0x4d]	1416343	1			T3	9		T50	23		T52	5
valid_sources[0x4e]	2241178	1			T3	7		T50	30		T52	11
valid_sources[0x4f]	1317363	1			T1	2		T3	9		T50	38
valid_sources[0x50]	3268616	1			T3	2		T50	30		T51	2
valid_sources[0x51]	1318776	1			T3	5		T50	32		T52	7
valid_sources[0x52]	1342345	1			T3	2		T48	40		T50	34
valid_sources[0x53]	1315655	1			T1	2		T3	2		T50	34
valid_sources[0x54]	1312962	1			T3	2		T50	31		T52	7
valid_sources[0x55]	1327709	1			T3	9		T49	21		T50	22
valid_sources[0x56]	3135860	1			T1	3		T3	5		T47	1
valid_sources[0x57]	1351653	1			T1	1		T3	7		T48	15
valid_sources[0x58]	1320809	1			T1	1		T3	5		T50	27
valid_sources[0x59]	1322548	1			T3	9		T50	22		T52	4
valid_sources[0x5a]	1595396	1			T3	3		T50	28		T52	6
valid_sources[0x5b]	1444610	1			T3	6		T50	27		T52	3
valid_sources[0x5c]	1596921	1			T3	6		T50	25		T52	3
valid_sources[0x5d]	1349556	1			T3	5		T50	30		T52	6
valid_sources[0x5e]	1328672	1			T1	3		T3	7		T49	23
valid_sources[0x5f]	4796389	1			T1	2		T3	5		T50	30
valid_sources[0x60]	1313279	1			T3	6		T50	27		T52	4
valid_sources[0x61]	1321056	1			T1	1		T3	7		T47	1
valid_sources[0x62]	4933833	1			T3	3		T50	22		T52	4
valid_sources[0x63]	2310685	1			T3	4		T50	16		T52	1
valid_sources[0x64]	1326649	1			T1	1		T3	4		T50	27
valid_sources[0x65]	1617799	1			T3	5		T50	29		T52	2
valid_sources[0x66]	1362577	1			T3	6		T49	29		T50	24
valid_sources[0x67]	3133416	1			T3	4		T50	25		T52	5
valid_sources[0x68]	1980820	1			T1	1		T3	7		T49	50
valid_sources[0x69]	1331037	1			T3	5		T48	11		T50	29
valid_sources[0x6a]	1329469	1			T3	5		T48	10		T50	32
valid_sources[0x6b]	1318852	1			T1	1		T3	9		T50	32
valid_sources[0x6c]	1325474	1			T1	1		T3	6		T50	26
valid_sources[0x6d]	1324441	1			T3	6		T50	35		T52	2
valid_sources[0x6e]	1321391	1			T1	1		T3	5		T47	1
valid_sources[0x6f]	1323818	1			T1	1		T3	3		T50	20
valid_sources[0x70]	3457320	1			T3	6		T50	33		T52	4
valid_sources[0x71]	2199701	1			T3	2		T50	27		T52	4
valid_sources[0x72]	1320616	1			T1	1		T3	10		T50	37
valid_sources[0x73]	1344102	1			T3	6		T50	25		T52	2
valid_sources[0x74]	2430174	1			T3	6		T50	24		T52	5
valid_sources[0x75]	1784856	1			T1	1		T3	5		T50	28
valid_sources[0x76]	3729961	1			T3	5		T50	29		T55	1
valid_sources[0x77]	1316841	1			T3	6		T49	50		T50	29
valid_sources[0x78]	1316435	1			T1	1		T3	5		T50	26
valid_sources[0x79]	1321767	1			T3	8		T50	44		T52	6
valid_sources[0x7a]	1317232	1			T3	6		T50	22		T52	7
valid_sources[0x7b]	2338744	1			T3	4		T50	22		T52	2
valid_sources[0x7c]	1495361	1			T3	2		T50	31		T52	3
valid_sources[0x7d]	1323674	1			T3	5		T50	30		T52	5
valid_sources[0x7e]	1320323	1			T1	1		T3	2		T47	3
valid_sources[0x7f]	1320321	1			T3	4		T50	30		T64	2
valid_sources[0x80]	5235140	1			T3	4		T47	4		T48	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73557767

1

T1

40

T2

67

T3

533

values[0x0]

all_enables

biggest_size

62475122

1

T1

32

T2

2

T3

268

values[0x1]

all_enables

biggest_size

53972695

1

T1

21

T2

2

T3

256