Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

269539424

1

T1

37

T2

82

T3

371

full_word

190460632

1

T1

93

T2

71

T3

1057

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	459999746	1			T1	130		T2	153		T3	1428
auto[TlIntgErrCmd]	97	1			T49	6		T67	8		T110	8
auto[TlIntgErrData]	106	1			T49	2		T67	6		T110	5
auto[TlIntgErrBoth]	107	1			T49	2		T67	6		T110	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235395824

1

T1

70

T2

143

T3

882

auto[1]

224604232

1

T1

60

T2

10

T3

546

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161723706	1			T1	30		T2	76		T3	349
auto[TlIntgErrNone]	partial	auto[1]	107815435	1			T1	7		T2	6		T3	22
auto[TlIntgErrNone]	full_word	auto[0]	73671985	1			T1	40		T2	67		T3	533
auto[TlIntgErrNone]	full_word	auto[1]	116788620	1			T1	53		T2	4		T3	524
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T49	2		T67	3		T110	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T49	2		T67	4		T110	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T49	1		T110	1		T148	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T49	1		T67	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T49	1		T67	2		T110	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T67	2		T110	4		T112	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T49	1		T111	1		T147	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T67	2		T149	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T49	1		T67	2		T110	1
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T49	1		T67	3		T110	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T67	1		T111	2		T151	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T152	1		-	-		-	-