Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	117128367	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1264	1264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117128367	0	0
T53	7504	167	0	0
T54	1530	139	0	0
T55	2557	89	0	0
T56	2772	975	0	0
T57	0	453	0	0
T58	0	430	0	0
T59	0	182	0	0
T60	0	533	0	0
T63	3341	0	0	0
T64	6262	0	0	0
T65	2460	0	0	0
T66	1632	0	0	0
T67	9194	0	0	0
T68	2469	0	0	0
T69	0	139	0	0
T70	0	326	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1264	1264	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	216811587	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1264	1264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	216811587	0	0
T53	7504	166	0	0
T54	1530	116	0	0
T55	2557	82	0	0
T56	2772	552	0	0
T57	0	345	0	0
T58	0	421	0	0
T59	0	180	0	0
T60	0	321	0	0
T63	3341	0	0	0
T64	6262	0	0	0
T65	2460	0	0	0
T66	1632	0	0	0
T67	9194	0	0	0
T68	2469	0	0	0
T69	0	208	0	0
T70	0	170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1264	1264	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	326430569	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1264	1264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	326430569	0	0
T1	1755	139	0	0
T2	5040	306	0	0
T3	10776	1610	0	0
T47	1005	40	0	0
T48	3656	337	0	0
T49	10302	1505	0	0
T50	15318	13813	0	0
T51	1554	22	0	0
T52	10422	2064	0	0
T53	7504	472	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1264	1264	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	612461423	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1264	1264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	612461423	0	0
T1	1755	130	0	0
T2	5040	812	0	0
T3	10776	1428	0	0
T47	1005	40	0	0
T48	3656	305	0	0
T49	10302	1380	0	0
T50	15318	6965	0	0
T51	1554	22	0	0
T52	10422	3714	0	0
T53	7504	452	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1755	1655	0	0
T2	5040	4814	0	0
T3	10776	10232	0	0
T47	1005	936	0	0
T48	3656	3229	0	0
T49	10302	9463	0	0
T50	15318	15228	0	0
T51	1554	1458	0	0
T52	10422	10371	0	0
T53	7504	7404	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1264	1264	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0