Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258480728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

186155422

1

T1

97

T2

1903

T3

210

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230152153	1			T1	71		T2	1536		T3	163
values[0x0]	102962193	1			T1	32		T2	593		T3	164
values[0x1]	111521804	1			T1	28		T2	614		T3	306

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200730320	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

243905830

1

T1

107

T2

2168

T3

392

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1524880	1			T1	1		T2	18		T54	1
valid_sources[0x01]	1321266	1			T2	16		T55	7		T57	3
valid_sources[0x02]	1317443	1			T2	12		T55	1		T57	3
valid_sources[0x03]	1350194	1			T1	2		T2	10		T89	2
valid_sources[0x04]	4643166	1			T2	8		T55	6		T59	2
valid_sources[0x05]	2345671	1			T2	2		T55	5		T59	4
valid_sources[0x06]	1324107	1			T1	3		T2	8		T55	4
valid_sources[0x07]	1321305	1			T2	9		T55	10		T58	54
valid_sources[0x08]	1316279	1			T2	18		T55	6		T59	1
valid_sources[0x09]	2263314	1			T1	2		T2	10		T55	4
valid_sources[0x0a]	1524835	1			T1	3		T2	9		T55	8
valid_sources[0x0b]	1317484	1			T2	10		T55	1		T57	5
valid_sources[0x0c]	1319270	1			T2	6		T55	9		T57	1
valid_sources[0x0d]	1425965	1			T1	1		T2	15		T58	21
valid_sources[0x0e]	1322673	1			T2	9		T54	1		T55	7
valid_sources[0x0f]	1321861	1			T1	1		T2	11		T55	4
valid_sources[0x10]	1322237	1			T2	5		T58	47		T59	1
valid_sources[0x11]	1333161	1			T2	21		T57	2		T59	3
valid_sources[0x12]	1322087	1			T2	16		T56	7		T57	5
valid_sources[0x13]	1330181	1			T2	9		T55	8		T59	2
valid_sources[0x14]	1321230	1			T2	16		T59	3		T89	3
valid_sources[0x15]	1425630	1			T2	12		T3	9		T54	1
valid_sources[0x16]	1310038	1			T2	17		T3	21		T55	1
valid_sources[0x17]	3262360	1			T2	8		T3	100		T55	6
valid_sources[0x18]	3261946	1			T1	4		T2	7		T55	3
valid_sources[0x19]	1316955	1			T1	5		T2	8		T55	1
valid_sources[0x1a]	1326900	1			T1	2		T2	8		T3	31
valid_sources[0x1b]	1318668	1			T2	14		T3	7		T55	9
valid_sources[0x1c]	1345019	1			T1	7		T2	9		T59	5
valid_sources[0x1d]	1897244	1			T1	3		T2	15		T55	5
valid_sources[0x1e]	1320374	1			T2	8		T55	13		T59	3
valid_sources[0x1f]	1322198	1			T2	9		T55	6		T57	3
valid_sources[0x20]	1321310	1			T2	4		T55	8		T59	1
valid_sources[0x21]	2223528	1			T2	6		T55	3		T59	3
valid_sources[0x22]	3305139	1			T2	9		T54	1		T55	5
valid_sources[0x23]	1314410	1			T1	2		T2	11		T55	7
valid_sources[0x24]	1315172	1			T1	5		T2	12		T55	1
valid_sources[0x25]	1322658	1			T2	11		T55	4		T59	1
valid_sources[0x26]	1313789	1			T1	2		T2	12		T55	3
valid_sources[0x27]	3064141	1			T1	1		T2	6		T55	8
valid_sources[0x28]	4226469	1			T1	1		T2	12		T54	1
valid_sources[0x29]	1322722	1			T2	10		T54	1		T55	8
valid_sources[0x2a]	1426361	1			T2	15		T60	1		T89	3
valid_sources[0x2b]	1312858	1			T2	10		T54	1		T55	8
valid_sources[0x2c]	1318334	1			T2	9		T55	9		T56	1
valid_sources[0x2d]	3832064	1			T2	9		T54	1		T55	3
valid_sources[0x2e]	1316988	1			T2	15		T55	2		T59	1
valid_sources[0x2f]	1921630	1			T2	12		T54	1		T55	2
valid_sources[0x30]	2799429	1			T2	2		T3	129		T55	7
valid_sources[0x31]	1940803	1			T2	11		T55	7		T89	1
valid_sources[0x32]	1323243	1			T2	6		T55	3		T57	8
valid_sources[0x33]	1315856	1			T2	7		T58	138		T59	3
valid_sources[0x34]	2227612	1			T2	2		T55	2		T59	2
valid_sources[0x35]	1314940	1			T2	26		T55	2		T56	2
valid_sources[0x36]	2164030	1			T2	22		T89	3		T127	5
valid_sources[0x37]	1321107	1			T2	13		T57	3		T59	1
valid_sources[0x38]	1771542	1			T1	2		T2	5		T55	10
valid_sources[0x39]	1312273	1			T2	23		T55	4		T57	2
valid_sources[0x3a]	1314324	1			T1	6		T2	7		T55	11
valid_sources[0x3b]	1964292	1			T2	12		T55	7		T58	10
valid_sources[0x3c]	1317419	1			T2	14		T55	4		T57	2
valid_sources[0x3d]	1427798	1			T2	5		T55	6		T58	12
valid_sources[0x3e]	3666913	1			T2	12		T55	3		T57	8
valid_sources[0x3f]	2176498	1			T2	6		T55	3		T59	4
valid_sources[0x40]	1318155	1			T2	16		T55	36		T58	48
valid_sources[0x41]	1312536	1			T2	7		T3	17		T55	9
valid_sources[0x42]	1323870	1			T2	6		T55	1		T59	1
valid_sources[0x43]	1317346	1			T2	5		T55	15		T57	5
valid_sources[0x44]	1317066	1			T2	5		T55	5		T57	2
valid_sources[0x45]	1412842	1			T1	1		T2	6		T56	2
valid_sources[0x46]	1313056	1			T2	16		T55	1		T57	2
valid_sources[0x47]	3651320	1			T2	11		T55	1		T59	1
valid_sources[0x48]	1318959	1			T2	5		T55	1		T57	4
valid_sources[0x49]	1313336	1			T2	14		T3	4		T55	7
valid_sources[0x4a]	1310140	1			T2	9		T55	31		T57	1
valid_sources[0x4b]	1317178	1			T1	3		T2	16		T89	4
valid_sources[0x4c]	1315911	1			T2	9		T59	3		T89	18
valid_sources[0x4d]	1330328	1			T1	1		T2	15		T54	1
valid_sources[0x4e]	1314801	1			T2	5		T58	68		T59	3
valid_sources[0x4f]	1322324	1			T1	3		T2	8		T55	2
valid_sources[0x50]	2017965	1			T2	16		T55	13		T89	3
valid_sources[0x51]	1318048	1			T2	28		T55	11		T57	2
valid_sources[0x52]	1449029	1			T1	2		T2	15		T59	3
valid_sources[0x53]	1318627	1			T2	8		T55	5		T59	2
valid_sources[0x54]	1317184	1			T1	4		T2	2		T54	1
valid_sources[0x55]	1320331	1			T2	8		T57	4		T59	2
valid_sources[0x56]	1343579	1			T2	11		T54	1		T55	8
valid_sources[0x57]	1328832	1			T2	18		T55	3		T59	1
valid_sources[0x58]	1365498	1			T2	8		T58	20		T59	2
valid_sources[0x59]	2169165	1			T2	12		T55	4		T59	1
valid_sources[0x5a]	1498845	1			T2	18		T55	11		T57	1
valid_sources[0x5b]	4138844	1			T2	2		T59	1		T89	3
valid_sources[0x5c]	1313687	1			T2	7		T55	1		T57	1
valid_sources[0x5d]	1318513	1			T1	1		T2	8		T54	1
valid_sources[0x5e]	1323482	1			T2	14		T54	2		T57	2
valid_sources[0x5f]	3060762	1			T1	2		T2	10		T55	7
valid_sources[0x60]	3734081	1			T2	10		T54	1		T55	4
valid_sources[0x61]	1320378	1			T2	14		T55	4		T56	1
valid_sources[0x62]	1317614	1			T1	3		T2	19		T54	1
valid_sources[0x63]	1319795	1			T2	10		T59	1		T89	3
valid_sources[0x64]	1316729	1			T2	11		T55	5		T59	2
valid_sources[0x65]	4100971	1			T2	8		T59	2		T89	4
valid_sources[0x66]	1313612	1			T2	3		T55	7		T59	2
valid_sources[0x67]	1316166	1			T2	6		T55	1		T59	5
valid_sources[0x68]	1508380	1			T1	2		T2	3		T54	2
valid_sources[0x69]	1313794	1			T1	5		T2	11		T55	4
valid_sources[0x6a]	2212930	1			T2	2		T55	2		T56	2
valid_sources[0x6b]	1321192	1			T2	13		T55	1		T59	3
valid_sources[0x6c]	1401782	1			T2	9		T54	1		T57	3
valid_sources[0x6d]	1310727	1			T2	6		T55	1		T59	1
valid_sources[0x6e]	1758764	1			T2	9		T55	9		T57	1
valid_sources[0x6f]	1321190	1			T2	12		T55	10		T57	4
valid_sources[0x70]	1311080	1			T2	12		T55	7		T57	6
valid_sources[0x71]	1917135	1			T2	7		T89	7		T127	4
valid_sources[0x72]	1391699	1			T2	6		T55	1		T59	1
valid_sources[0x73]	1321010	1			T2	12		T55	2		T57	3
valid_sources[0x74]	1315357	1			T1	7		T2	21		T54	1
valid_sources[0x75]	1417775	1			T2	18		T55	2		T59	2
valid_sources[0x76]	1330578	1			T2	6		T57	1		T59	1
valid_sources[0x77]	1313888	1			T2	16		T55	2		T59	2
valid_sources[0x78]	1978844	1			T2	10		T55	2		T89	6
valid_sources[0x79]	1313824	1			T2	11		T55	2		T57	1
valid_sources[0x7a]	1973749	1			T2	2		T55	3		T57	7
valid_sources[0x7b]	1362933	1			T1	1		T2	7		T89	9
valid_sources[0x7c]	1321264	1			T2	10		T55	4		T57	2
valid_sources[0x7d]	4531730	1			T1	2		T2	9		T55	3
valid_sources[0x7e]	1319124	1			T2	12		T3	20		T55	1
valid_sources[0x7f]	1326790	1			T2	9		T3	1		T54	1
valid_sources[0x80]	1342404	1			T2	4		T55	12		T57	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72372664

1

T1

42

T2

789

T3

88

values[0x0]

all_enables

biggest_size

61101270

1

T1

28

T2

546

T3

64

values[0x1]

all_enables

biggest_size

52681488

1

T1

27

T2

568

T3

58