Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

264556221

1

T1

34

T2

844

T3

547

full_word

186531175

1

T1

97

T2

1903

T3

217

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451087066	1			T1	131		T2	2727		T3	764
auto[TlIntgErrCmd]	115	1			T2	5		T58	7		T104	4
auto[TlIntgErrData]	100	1			T2	5		T58	8		T104	2
auto[TlIntgErrBoth]	115	1			T2	10		T58	5		T104	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231303715

1

T1

71

T2

1539

T3

220

auto[1]

219783681

1

T1

60

T2

1208

T3

544

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158837312	1			T1	29		T2	738		T3	129
auto[TlIntgErrNone]	partial	auto[1]	105718597	1			T1	5		T2	86		T3	418
auto[TlIntgErrNone]	full_word	auto[0]	72466265	1			T1	42		T2	789		T3	91
auto[TlIntgErrNone]	full_word	auto[1]	114064892	1			T1	55		T2	1114		T3	126
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T2	3		T58	2		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T2	2		T58	4		T104	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T58	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T128	2		T169	1		T170	2
auto[TlIntgErrData]	partial	auto[0]	48	1			T2	2		T58	3		T104	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T2	3		T58	3		T104	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T58	1		T145	1		T171	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T58	1		T128	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T2	7		T58	2		T104	1
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T2	3		T58	3		T104	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T168	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T131	1		T173	1		T145	1