Module Definition
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Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sha3_done_sender 100.00 100.00 100.00 100.00
tb.dut.gen_entropy.u_entropy.u_entropy_configured 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_sha3_done_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.56 98.77 96.05 100.00 100.00 96.55 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00


Module Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.15 100.00 95.74 100.00 100.00 100.00 gen_entropy.u_entropy


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1

Branch Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 1308466 1308454 0 0
T5 141310 141174 0 0
T6 8266 7988 0 0
T10 306834 306832 0 0
T11 46196 46058 0 0
T18 476514 476320 0 0
T19 534382 534278 0 0
T20 1739242 1739222 0 0
T21 1316958 1316944 0 0
T25 2996 2852 0 0

Line Coverage for Instance : tb.dut.u_sha3_done_sender
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1

Branch Coverage for Instance : tb.dut.u_sha3_done_sender
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sha3_done_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 654233 654227 0 0
T5 70655 70587 0 0
T6 4133 3994 0 0
T10 153417 153416 0 0
T11 23098 23029 0 0
T18 238257 238160 0 0
T19 267191 267139 0 0
T20 869621 869611 0 0
T21 658479 658472 0 0
T25 1498 1426 0 0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1

Branch Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 654233 654227 0 0
T5 70655 70587 0 0
T6 4133 3994 0 0
T10 153417 153416 0 0
T11 23098 23029 0 0
T18 238257 238160 0 0
T19 267191 267139 0 0
T20 869621 869611 0 0
T21 658479 658472 0 0
T25 1498 1426 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%