Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	113290400	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	113290400	0	0
T3	2663	901	0	0
T54	1469	0	0	0
T55	11536	0	0	0
T56	918	0	0	0
T57	3131	264	0	0
T58	9311	0	0	0
T59	4150	522	0	0
T60	1011	0	0	0
T61	0	247	0	0
T62	1555	349	0	0
T63	0	108	0	0
T64	0	71	0	0
T65	0	333	0	0
T66	0	171	0	0
T67	0	300	0	0
T69	661	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	209019824	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	209019824	0	0
T3	2663	493	0	0
T54	1469	0	0	0
T55	11536	0	0	0
T56	918	0	0	0
T57	3131	605	0	0
T58	9311	0	0	0
T59	4150	383	0	0
T60	1011	0	0	0
T61	0	866	0	0
T62	1555	206	0	0
T63	0	271	0	0
T64	0	37	0	0
T65	0	326	0	0
T66	0	397	0	0
T67	0	295	0	0
T69	661	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	319937764	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	319937764	0	0
T1	1658	146	0	0
T2	28308	2986	0	0
T3	2663	349	0	0
T54	1469	40	0	0
T55	11536	2818	0	0
T56	918	22	0	0
T57	3131	340	0	0
T58	9311	5346	0	0
T59	4150	1553	0	0
T60	1011	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	597077452	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	597077452	0	0
T1	1658	131	0	0
T2	28308	2747	0	0
T3	2663	218	0	0
T54	1469	40	0	0
T55	11536	5915	0	0
T56	918	22	0	0
T57	3131	790	0	0
T58	9311	2756	0	0
T59	4150	930	0	0
T60	1011	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1658	1603	0	0
T2	28308	26729	0	0
T3	2663	2590	0	0
T54	1469	1417	0	0
T55	11536	11350	0	0
T56	918	825	0	0
T57	3131	3049	0	0
T58	9311	7712	0	0
T59	4150	4075	0	0
T60	1011	957	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0