Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1370590	0	0
entropy_period_rd_A	2147483647	2425	0	0
intr_enable_rd_A	2147483647	3407	0	0
prefix_0_rd_A	2147483647	2567	0	0
prefix_10_rd_A	2147483647	2569	0	0
prefix_1_rd_A	2147483647	2548	0	0
prefix_2_rd_A	2147483647	2542	0	0
prefix_3_rd_A	2147483647	2482	0	0
prefix_4_rd_A	2147483647	2568	0	0
prefix_5_rd_A	2147483647	2531	0	0
prefix_6_rd_A	2147483647	2512	0	0
prefix_7_rd_A	2147483647	2680	0	0
prefix_8_rd_A	2147483647	2577	0	0
prefix_9_rd_A	2147483647	2487	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1370590	0	0
T2	28308	4	0	0
T3	2663	17	0	0
T54	1469	0	0	0
T55	11536	0	0	0
T56	918	0	0	0
T57	3131	0	0	0
T58	9311	1	0	0
T59	4150	335	0	0
T60	1011	0	0	0
T61	0	80	0	0
T62	1555	0	0	0
T64	0	1	0	0
T65	0	167	0	0
T104	0	2	0	0
T128	0	4	0	0
T130	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2425	0	0
T55	11536	78	0	0
T56	918	0	0	0
T57	3131	7	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	3	0	0
T69	661	0	0	0
T89	8449	59	0	0
T90	0	27	0	0
T92	0	7	0	0
T127	9090	0	0	0
T135	0	1	0	0
T136	0	8	0	0
T137	0	62	0	0
T155	0	61	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3407	0	0
T55	11536	61	0	0
T56	918	0	0	0
T57	3131	8	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	2	0	0
T69	661	0	0	0
T89	8449	40	0	0
T90	0	66	0	0
T115	0	13	0	0
T127	9090	0	0	0
T135	0	13	0	0
T156	0	11	0	0
T157	0	5	0	0
T158	0	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2567	0	0
T55	11536	67	0	0
T56	918	0	0	0
T57	3131	1	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	1	0	0
T69	661	0	0	0
T89	8449	11	0	0
T90	0	12	0	0
T92	0	6	0	0
T127	9090	0	0	0
T135	0	10	0	0
T136	0	6	0	0
T137	0	53	0	0
T155	0	18	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2569	0	0
T55	11536	55	0	0
T56	918	0	0	0
T57	3131	10	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	6	0	0
T69	661	0	0	0
T89	8449	45	0	0
T90	0	25	0	0
T92	0	6	0	0
T127	9090	0	0	0
T135	0	3	0	0
T136	0	1	0	0
T137	0	49	0	0
T155	0	25	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2548	0	0
T55	11536	41	0	0
T56	918	0	0	0
T57	3131	1	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	3	0	0
T69	661	0	0	0
T89	8449	35	0	0
T90	0	37	0	0
T92	0	6	0	0
T127	9090	0	0	0
T135	0	9	0	0
T136	0	3	0	0
T137	0	66	0	0
T155	0	47	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2542	0	0
T55	11536	31	0	0
T56	918	0	0	0
T57	3131	11	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	3	0	0
T69	661	0	0	0
T89	8449	23	0	0
T90	0	10	0	0
T92	0	6	0	0
T127	9090	0	0	0
T135	0	12	0	0
T136	0	6	0	0
T137	0	54	0	0
T155	0	24	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2482	0	0
T55	11536	36	0	0
T56	918	0	0	0
T57	3131	5	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	1	0	0
T66	0	1	0	0
T69	661	0	0	0
T89	8449	24	0	0
T90	0	29	0	0
T127	9090	0	0	0
T135	0	7	0	0
T136	0	3	0	0
T137	0	60	0	0
T155	0	45	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2568	0	0
T55	11536	51	0	0
T56	918	0	0	0
T57	3131	18	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	6	0	0
T69	661	0	0	0
T89	8449	28	0	0
T90	0	35	0	0
T92	0	1	0	0
T127	9090	0	0	0
T135	0	11	0	0
T136	0	9	0	0
T137	0	33	0	0
T155	0	35	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2531	0	0
T55	11536	42	0	0
T56	918	0	0	0
T57	3131	6	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	9	0	0
T66	0	7	0	0
T69	661	0	0	0
T89	8449	42	0	0
T90	0	37	0	0
T92	0	3	0	0
T127	9090	0	0	0
T135	0	13	0	0
T137	0	55	0	0
T155	0	25	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2512	0	0
T55	11536	48	0	0
T56	918	0	0	0
T57	3131	8	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	5	0	0
T69	661	0	0	0
T89	8449	39	0	0
T90	0	22	0	0
T92	0	6	0	0
T127	9090	0	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	46	0	0
T155	0	18	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2680	0	0
T55	11536	45	0	0
T56	918	0	0	0
T57	3131	7	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T66	0	5	0	0
T69	661	0	0	0
T89	8449	40	0	0
T90	0	24	0	0
T92	0	7	0	0
T127	9090	0	0	0
T135	0	7	0	0
T136	0	9	0	0
T137	0	40	0	0
T155	0	24	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2577	0	0
T55	11536	53	0	0
T56	918	0	0	0
T57	3131	4	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	4	0	0
T69	661	0	0	0
T89	8449	32	0	0
T90	0	39	0	0
T92	0	4	0	0
T127	9090	0	0	0
T135	0	9	0	0
T136	0	1	0	0
T137	0	64	0	0
T155	0	17	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2487	0	0
T55	11536	30	0	0
T56	918	0	0	0
T57	3131	6	0	0
T58	9311	0	0	0
T59	4150	0	0	0
T60	1011	0	0	0
T62	1555	0	0	0
T63	0	7	0	0
T69	661	0	0	0
T89	8449	36	0	0
T90	0	22	0	0
T92	0	1	0	0
T127	9090	0	0	0
T135	0	8	0	0
T136	0	5	0	0
T137	0	53	0	0
T155	0	24	0	0