Unified Coverage Report :: Module :: prim_generic_flop_en

Module : prim_generic_flop_en

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_flop_en

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_flop_en

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
32	1	1
33	1	1
34	1	1
35	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	34	if (en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T10,T11
0	0	Covered	T4,T5,T6