SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[0].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[1].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 56605 | 1 | T2 | 5 | T36 | 1175 | T39 | 844 | ||||
auto[1] | 22106 | 1 | T2 | 5 | T36 | 24 | T7 | 1 | ||||
auto[2] | 281080 | 1 | T2 | 446 | T36 | 4120 | T39 | 2864 | ||||
auto[3] | 302019 | 1 | T2 | 451 | T36 | 4154 | T39 | 2892 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 31850 | 1 | T2 | 4 | T36 | 423 | T39 | 685 | ||||
auto[1] | 9273 | 1 | T2 | 4 | T36 | 12 | T7 | 1 | ||||
auto[2] | 152441 | 1 | T2 | 292 | T36 | 1492 | T39 | 2363 | ||||
auto[3] | 160863 | 1 | T2 | 296 | T36 | 1511 | T39 | 2388 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 30781 | 1 | T2 | 3 | T3 | 1 | T36 | 310 | ||||
auto[1] | 10823 | 1 | T2 | 3 | T3 | 1 | T36 | 6 | ||||
auto[2] | 144623 | 1 | T2 | 147 | T3 | 38 | T36 | 1078 | ||||
auto[3] | 154601 | 1 | T2 | 150 | T3 | 39 | T36 | 1089 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |