Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	263320798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187683526

1

T1

805232

T2

17341

T3

12848

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	233936435	1			T1	105065		T2	23760		T3	14533
values[0x0]	104260912	1			T1	458171		T2	5009		T3	3320
values[0x1]	112806977	1			T1	499745		T2	5396		T3	3753

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	204591661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

246412663

1

T1

107637

T2

21696

T3

14971

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1370971	1			T1	7854		T2	10		T3	91
valid_sources[0x01]	1482654	1			T1	7888		T2	6		T3	94
valid_sources[0x02]	1366176	1			T1	7589		T2	3		T3	93
valid_sources[0x03]	2202018	1			T1	7710		T2	15		T3	66
valid_sources[0x04]	1571425	1			T1	7672		T2	9		T3	87
valid_sources[0x05]	1449643	1			T1	8105		T2	6		T3	72
valid_sources[0x06]	2207925	1			T1	7841		T2	4		T3	93
valid_sources[0x07]	1823247	1			T1	7719		T2	4		T3	95
valid_sources[0x08]	2266194	1			T1	7907		T2	4		T3	94
valid_sources[0x09]	1368307	1			T1	8022		T2	11		T3	98
valid_sources[0x0a]	1516317	1			T1	7852		T2	14		T3	89
valid_sources[0x0b]	2041206	1			T1	7768		T2	6		T3	74
valid_sources[0x0c]	1366859	1			T1	7793		T2	5		T3	81
valid_sources[0x0d]	1360727	1			T1	7750		T2	7		T3	106
valid_sources[0x0e]	1370188	1			T1	7876		T2	5		T3	85
valid_sources[0x0f]	1495612	1			T1	7943		T2	5		T3	70
valid_sources[0x10]	1841305	1			T1	7843		T2	11		T3	82
valid_sources[0x11]	1364339	1			T1	7864		T2	8		T3	79
valid_sources[0x12]	2309810	1			T1	7860		T2	6		T3	101
valid_sources[0x13]	1380974	1			T1	7796		T2	10		T3	79
valid_sources[0x14]	1367908	1			T1	7801		T2	10		T3	69
valid_sources[0x15]	2429631	1			T1	7925		T2	13		T3	80
valid_sources[0x16]	1369058	1			T1	7953		T2	3		T3	88
valid_sources[0x17]	2206049	1			T1	7921		T2	7		T3	82
valid_sources[0x18]	2304467	1			T1	7915		T2	7		T3	75
valid_sources[0x19]	1372283	1			T1	7916		T2	7		T3	84
valid_sources[0x1a]	1413707	1			T1	8051		T2	11		T3	69
valid_sources[0x1b]	1372841	1			T1	7866		T2	6		T3	94
valid_sources[0x1c]	2298382	1			T1	7996		T2	6		T3	90
valid_sources[0x1d]	1370381	1			T1	7577		T2	12		T3	74
valid_sources[0x1e]	1367904	1			T1	7835		T2	5		T3	95
valid_sources[0x1f]	1543378	1			T1	7790		T2	13		T3	91
valid_sources[0x20]	1369130	1			T1	7826		T2	8		T3	78
valid_sources[0x21]	1373091	1			T1	7806		T2	9		T3	93
valid_sources[0x22]	1365798	1			T1	7937		T2	8		T3	81
valid_sources[0x23]	1408806	1			T1	7822		T2	3		T3	93
valid_sources[0x24]	1391928	1			T1	7964		T2	7		T3	87
valid_sources[0x25]	1370793	1			T1	7808		T2	7		T3	86
valid_sources[0x26]	1370166	1			T1	7829		T2	11		T3	86
valid_sources[0x27]	2213533	1			T1	7743		T2	6		T3	73
valid_sources[0x28]	1363335	1			T1	8125		T2	5		T3	66
valid_sources[0x29]	3714873	1			T1	7877		T2	9		T3	78
valid_sources[0x2a]	1369562	1			T1	8047		T2	6		T3	70
valid_sources[0x2b]	1515967	1			T1	7783		T2	5		T3	80
valid_sources[0x2c]	2273437	1			T1	7908		T2	6		T3	86
valid_sources[0x2d]	1367887	1			T1	8002		T2	6		T3	73
valid_sources[0x2e]	1369900	1			T1	8032		T2	7		T3	98
valid_sources[0x2f]	1366806	1			T1	7875		T2	4		T3	67
valid_sources[0x30]	1377285	1			T1	7920		T2	9		T3	109
valid_sources[0x31]	2025106	1			T1	7644		T2	4		T3	89
valid_sources[0x32]	1369227	1			T1	7962		T2	7		T3	86
valid_sources[0x33]	1366141	1			T1	7812		T2	5		T3	78
valid_sources[0x34]	1369630	1			T1	7830		T2	7		T3	101
valid_sources[0x35]	1368752	1			T1	7695		T2	7		T3	94
valid_sources[0x36]	1790685	1			T1	7749		T2	10		T3	62
valid_sources[0x37]	1367597	1			T1	7671		T2	12		T3	95
valid_sources[0x38]	1372840	1			T1	7847		T2	5		T3	80
valid_sources[0x39]	1382592	1			T1	7670		T2	5		T3	80
valid_sources[0x3a]	3827744	1			T1	7928		T2	8		T3	65
valid_sources[0x3b]	3847316	1			T1	7909		T2	7		T3	92
valid_sources[0x3c]	3535125	1			T1	7930		T2	5		T3	77
valid_sources[0x3d]	1382246	1			T1	8084		T2	6		T3	97
valid_sources[0x3e]	2213353	1			T1	7738		T2	14		T3	88
valid_sources[0x3f]	1469022	1			T1	7925		T2	6		T3	98
valid_sources[0x40]	2264492	1			T1	7725		T2	6		T3	114
valid_sources[0x41]	1372998	1			T1	7749		T2	5		T3	72
valid_sources[0x42]	1370625	1			T1	7907		T2	5		T3	98
valid_sources[0x43]	2238737	1			T1	7861		T2	7		T3	87
valid_sources[0x44]	1817425	1			T1	7814		T2	5		T3	78
valid_sources[0x45]	1374490	1			T1	7748		T2	10		T3	104
valid_sources[0x46]	1364839	1			T1	7808		T2	2		T3	82
valid_sources[0x47]	1364828	1			T1	7772		T2	5		T3	96
valid_sources[0x48]	1492634	1			T1	7727		T2	13		T3	91
valid_sources[0x49]	3436857	1			T1	7974		T2	5		T3	112
valid_sources[0x4a]	2377982	1			T1	7791		T2	7		T3	74
valid_sources[0x4b]	2466169	1			T1	7703		T2	7		T3	72
valid_sources[0x4c]	1363101	1			T1	7874		T2	7		T3	82
valid_sources[0x4d]	1401869	1			T1	7957		T2	5		T3	85
valid_sources[0x4e]	3680467	1			T1	7939		T2	8		T3	89
valid_sources[0x4f]	1372214	1			T1	7958		T2	9		T3	111
valid_sources[0x50]	1479125	1			T1	7883		T2	6		T3	86
valid_sources[0x51]	1364055	1			T1	7741		T2	8		T3	91
valid_sources[0x52]	1371845	1			T1	7642		T2	4		T3	72
valid_sources[0x53]	1367776	1			T1	7805		T2	5		T3	77
valid_sources[0x54]	1372366	1			T1	7893		T2	5		T3	67
valid_sources[0x55]	1812057	1			T1	7775		T2	4		T3	74
valid_sources[0x56]	1370131	1			T1	8043		T2	2		T3	72
valid_sources[0x57]	3156384	1			T1	7902		T2	11		T3	67
valid_sources[0x58]	1823402	1			T1	7893		T2	5		T3	106
valid_sources[0x59]	1367422	1			T1	7824		T2	7		T3	73
valid_sources[0x5a]	1383127	1			T1	7989		T2	7		T3	104
valid_sources[0x5b]	3316031	1			T1	7916		T2	9		T3	88
valid_sources[0x5c]	2012870	1			T1	7829		T2	8		T3	93
valid_sources[0x5d]	1383484	1			T1	7884		T2	4		T3	85
valid_sources[0x5e]	1373138	1			T1	7749		T2	5		T3	88
valid_sources[0x5f]	1371807	1			T1	7781		T2	10		T3	48
valid_sources[0x60]	1366972	1			T1	7787		T2	5		T3	61
valid_sources[0x61]	1361744	1			T1	7787		T2	5		T3	82
valid_sources[0x62]	1366489	1			T1	7669		T2	6		T3	71
valid_sources[0x63]	1481148	1			T1	7677		T2	6		T3	78
valid_sources[0x64]	2719211	1			T1	7981		T2	10		T3	79
valid_sources[0x65]	1378707	1			T1	7986		T2	9		T3	101
valid_sources[0x66]	2231844	1			T1	7942		T2	10		T3	81
valid_sources[0x67]	1375872	1			T1	7859		T2	18		T3	85
valid_sources[0x68]	1541492	1			T1	7906		T2	7		T3	77
valid_sources[0x69]	1376381	1			T1	7742		T2	7		T3	92
valid_sources[0x6a]	1374220	1			T1	7871		T2	6		T3	104
valid_sources[0x6b]	1676316	1			T1	7711		T2	7		T3	105
valid_sources[0x6c]	3708035	1			T1	7898		T2	6		T3	82
valid_sources[0x6d]	1813988	1			T1	7805		T2	5		T3	74
valid_sources[0x6e]	1371031	1			T1	7904		T2	5		T3	93
valid_sources[0x6f]	2025790	1			T1	7911		T2	8		T3	73
valid_sources[0x70]	1371000	1			T1	7772		T2	9		T3	87
valid_sources[0x71]	1369644	1			T1	7885		T2	5		T3	85
valid_sources[0x72]	1366354	1			T1	7920		T2	7		T3	67
valid_sources[0x73]	1358541	1			T1	7770		T2	3		T3	67
valid_sources[0x74]	2129255	1			T1	7836		T2	7		T3	105
valid_sources[0x75]	2983184	1			T1	7770		T2	10		T3	61
valid_sources[0x76]	1391986	1			T1	7962		T2	7		T3	83
valid_sources[0x77]	6694370	1			T1	7825		T2	32291		T3	93
valid_sources[0x78]	1370162	1			T1	7930		T2	17		T3	53
valid_sources[0x79]	1368916	1			T1	7867		T2	11		T3	81
valid_sources[0x7a]	1369772	1			T1	7903		T2	9		T3	67
valid_sources[0x7b]	1371435	1			T1	7801		T2	8		T3	57
valid_sources[0x7c]	5718372	1			T1	7884		T2	11		T3	54
valid_sources[0x7d]	1365574	1			T1	7709		T2	8		T3	99
valid_sources[0x7e]	3686393	1			T1	7901		T2	6		T3	75
valid_sources[0x7f]	1369244	1			T1	7981		T2	9		T3	76
valid_sources[0x80]	3757420	1			T1	7845		T2	6		T3	82

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73006582

1

T1

327141

T2

11997

T3

8918

values[0x0]

all_enables

biggest_size

61622700

1

T1

258533

T2

2923

T3

2073

values[0x1]

all_enables

biggest_size

53054244

1

T1

219558

T2

2421

T3

1857