Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

266523940

1

T1

120334

T2

16824

T3

8758

full_word

187883454

1

T1

805232

T2

17341

T3

12848

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	454407114	1			T1	200857		T2	34165		T3	21606
auto[TlIntgErrCmd]	92	1			T134	5		T135	4		T136	7
auto[TlIntgErrData]	93	1			T134	3		T135	1		T136	1
auto[TlIntgErrBoth]	95	1			T134	2		T135	5		T136	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234550308

1

T1

105065

T2

23760

T3

14533

auto[1]

219857086

1

T1

957916

T2

10405

T3

7073

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161493370	1			T1	723518		T2	11763		T3	5615
auto[TlIntgErrNone]	partial	auto[1]	105030321	1			T1	479825		T2	5061		T3	3143
auto[TlIntgErrNone]	full_word	auto[0]	73056814	1			T1	327141		T2	11997		T3	8918
auto[TlIntgErrNone]	full_word	auto[1]	114826609	1			T1	478091		T2	5344		T3	3930
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T134	2		T136	3		T184	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T134	3		T135	3		T136	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T189	1		T190	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T135	1		T182	1		T183	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T134	2		T136	1		T186	1
auto[TlIntgErrData]	partial	auto[1]	31	1			T134	1		T182	1		T184	2
auto[TlIntgErrData]	full_word	auto[0]	10	1			T135	1		T183	1		T185	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T186	1		T191	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T135	3		T136	1		T186	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T134	1		T135	2		T136	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T134	1		T192	1		T190	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T182	1		T183	1		T191	1