Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	259880531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

185360492

1

T1

2

T2

843

T3

805831

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230991803	1			T1	1		T2	65		T3	103454
values[0x0]	102952547	1			T1	8		T2	444		T3	453171
values[0x1]	111296673	1			T1	17		T2	413		T3	488552

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201923584	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

243317439

1

T1

4

T2

865

T3

106596

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1299393	1			T1	2		T2	9		T3	7842
valid_sources[0x01]	1294447	1			T2	5		T3	7586		T8	21
valid_sources[0x02]	3306681	1			T2	1		T3	7737		T30	932
valid_sources[0x03]	1772738	1			T3	7710		T8	12		T30	506
valid_sources[0x04]	1304090	1			T2	2		T3	7694		T30	598
valid_sources[0x05]	1337051	1			T3	7871		T30	847		T32	102
valid_sources[0x06]	1305039	1			T3	7825		T8	48		T30	426
valid_sources[0x07]	1302355	1			T2	11		T3	7636		T8	92
valid_sources[0x08]	1307441	1			T2	1		T3	7719		T30	642
valid_sources[0x09]	1307046	1			T3	7624		T30	556		T32	73
valid_sources[0x0a]	1420004	1			T1	1		T2	9		T3	7689
valid_sources[0x0b]	1661478	1			T2	1		T3	7738		T30	562
valid_sources[0x0c]	1301812	1			T3	7739		T30	564		T32	50
valid_sources[0x0d]	1308651	1			T3	7578		T30	483		T32	83
valid_sources[0x0e]	1357193	1			T3	7662		T8	2		T30	1194
valid_sources[0x0f]	2187571	1			T2	3		T3	7618		T30	593
valid_sources[0x10]	1336178	1			T1	1		T2	1		T3	7602
valid_sources[0x11]	1298969	1			T2	4		T3	7838		T30	1072
valid_sources[0x12]	1541710	1			T3	7685		T30	218454		T32	76
valid_sources[0x13]	1309335	1			T2	12		T3	7546		T30	908
valid_sources[0x14]	1305770	1			T2	6		T3	7717		T30	621
valid_sources[0x15]	1391241	1			T3	7672		T8	42		T30	570
valid_sources[0x16]	2356193	1			T2	5		T3	7711		T30	584
valid_sources[0x17]	1297451	1			T2	2		T3	7753		T30	483
valid_sources[0x18]	1315246	1			T2	1		T3	7825		T8	29
valid_sources[0x19]	2191800	1			T3	7682		T30	542		T32	83
valid_sources[0x1a]	1312399	1			T2	3		T3	7624		T8	19
valid_sources[0x1b]	2083059	1			T3	7753		T30	579		T32	72
valid_sources[0x1c]	1302051	1			T2	2		T3	7726		T8	5
valid_sources[0x1d]	2851591	1			T3	7505		T8	5		T30	566
valid_sources[0x1e]	2628302	1			T2	2		T3	7840		T30	490
valid_sources[0x1f]	1303966	1			T2	3		T3	7697		T30	1225
valid_sources[0x20]	1355596	1			T3	7707		T30	567		T32	93
valid_sources[0x21]	1307197	1			T2	1		T3	7725		T30	598
valid_sources[0x22]	1301347	1			T2	8		T3	7738		T30	520
valid_sources[0x23]	1304487	1			T2	8		T3	7745		T30	566
valid_sources[0x24]	1505865	1			T2	5		T3	7789		T8	16
valid_sources[0x25]	4286538	1			T3	7660		T30	501		T32	75
valid_sources[0x26]	3651317	1			T2	2		T3	7628		T8	25
valid_sources[0x27]	3753981	1			T3	7615		T8	17		T30	545
valid_sources[0x28]	2194617	1			T3	7605		T30	608		T32	74
valid_sources[0x29]	2170257	1			T3	7717		T8	7		T30	494
valid_sources[0x2a]	1303213	1			T2	9		T3	7762		T30	665
valid_sources[0x2b]	2476046	1			T3	7658		T30	1304		T32	84
valid_sources[0x2c]	1300463	1			T2	1		T3	7724		T30	1803
valid_sources[0x2d]	1759525	1			T2	3		T3	7875		T30	467
valid_sources[0x2e]	1757569	1			T3	7650		T30	595		T32	62
valid_sources[0x2f]	1315081	1			T1	1		T2	1		T3	7759
valid_sources[0x30]	1418709	1			T2	12		T3	7902		T8	38
valid_sources[0x31]	1305152	1			T2	1		T3	7780		T30	609
valid_sources[0x32]	1297514	1			T2	6		T3	7770		T30	619
valid_sources[0x33]	1346792	1			T3	7738		T30	587		T32	67
valid_sources[0x34]	1302477	1			T2	2		T3	7745		T30	693
valid_sources[0x35]	2688262	1			T2	3		T3	7845		T30	1135
valid_sources[0x36]	1347935	1			T2	10		T3	8050		T8	5
valid_sources[0x37]	1754367	1			T2	7		T3	7669		T30	488
valid_sources[0x38]	2837537	1			T3	7745		T30	516		T32	68
valid_sources[0x39]	1306036	1			T2	3		T3	7684		T30	620
valid_sources[0x3a]	3282425	1			T2	4		T3	7725		T8	10
valid_sources[0x3b]	4279414	1			T3	7738		T8	7		T30	558
valid_sources[0x3c]	3657888	1			T2	1		T3	7785		T30	525
valid_sources[0x3d]	1305405	1			T2	3		T3	7759		T30	723
valid_sources[0x3e]	1312400	1			T3	7813		T8	3		T30	605
valid_sources[0x3f]	1297487	1			T2	4		T3	7778		T30	575
valid_sources[0x40]	1744916	1			T2	4		T3	7653		T8	15
valid_sources[0x41]	1415846	1			T2	3		T3	7715		T30	617
valid_sources[0x42]	1305845	1			T2	1		T3	7829		T30	689
valid_sources[0x43]	1304281	1			T3	7803		T30	511		T32	61
valid_sources[0x44]	1303484	1			T1	2		T2	5		T3	7658
valid_sources[0x45]	2126301	1			T2	3		T3	7619		T30	562
valid_sources[0x46]	1304205	1			T2	6		T3	7559		T30	714
valid_sources[0x47]	1299464	1			T2	7		T3	7779		T8	1
valid_sources[0x48]	2794694	1			T1	1		T2	2		T3	7775
valid_sources[0x49]	3658416	1			T2	5		T3	7788		T30	550
valid_sources[0x4a]	1311602	1			T2	10		T3	7669		T30	508
valid_sources[0x4b]	1436623	1			T2	3		T3	7732		T30	548
valid_sources[0x4c]	3264500	1			T3	7717		T7	195652		T30	597
valid_sources[0x4d]	1300698	1			T2	21		T3	7773		T30	460
valid_sources[0x4e]	1298174	1			T2	5		T3	7667		T30	563
valid_sources[0x4f]	1299526	1			T2	1		T3	7938		T30	677
valid_sources[0x50]	1507621	1			T2	4		T3	7891		T30	521
valid_sources[0x51]	2213356	1			T3	7850		T30	1491		T32	81
valid_sources[0x52]	1385412	1			T2	2		T3	7726		T8	4
valid_sources[0x53]	2256398	1			T2	2		T3	7730		T30	600
valid_sources[0x54]	1871466	1			T2	14		T3	7968		T30	560
valid_sources[0x55]	2108385	1			T3	7822		T8	12		T30	489
valid_sources[0x56]	1303965	1			T2	18		T3	7691		T30	666
valid_sources[0x57]	1303364	1			T2	5		T3	7859		T30	485
valid_sources[0x58]	1299137	1			T2	2		T3	7564		T30	482
valid_sources[0x59]	1303170	1			T2	2		T3	7509		T8	19
valid_sources[0x5a]	1302802	1			T2	4		T3	7627		T30	798
valid_sources[0x5b]	1296696	1			T3	7498		T30	555		T32	60
valid_sources[0x5c]	1962209	1			T2	19		T3	7666		T30	645
valid_sources[0x5d]	1766326	1			T2	5		T3	7763		T8	6
valid_sources[0x5e]	1301753	1			T3	7724		T8	30		T30	1071
valid_sources[0x5f]	1315018	1			T1	2		T2	5		T3	7723
valid_sources[0x60]	2180486	1			T3	7773		T8	15		T30	523
valid_sources[0x61]	1368072	1			T2	3		T3	7648		T30	1182
valid_sources[0x62]	3725598	1			T3	7806		T8	30		T30	707
valid_sources[0x63]	1305426	1			T3	7909		T8	19		T30	1170
valid_sources[0x64]	2050238	1			T2	4		T3	7647		T30	686
valid_sources[0x65]	1309900	1			T2	2		T3	7714		T8	12
valid_sources[0x66]	2376015	1			T3	7758		T30	523		T32	76
valid_sources[0x67]	1713774	1			T2	3		T3	7886		T8	10
valid_sources[0x68]	4765504	1			T1	3		T2	2		T3	7630
valid_sources[0x69]	1332098	1			T2	3		T3	7661		T30	580
valid_sources[0x6a]	1300654	1			T2	1		T3	7699		T8	8
valid_sources[0x6b]	1372681	1			T2	1		T3	7779		T8	32
valid_sources[0x6c]	3638095	1			T2	3		T3	7876		T30	646
valid_sources[0x6d]	1296946	1			T3	7985		T30	569		T32	70
valid_sources[0x6e]	1309566	1			T2	2		T3	7612		T30	559
valid_sources[0x6f]	1386282	1			T2	1		T3	7656		T8	17
valid_sources[0x70]	1302729	1			T3	7661		T8	9		T30	468
valid_sources[0x71]	2384208	1			T2	5		T3	7622		T8	56
valid_sources[0x72]	3753490	1			T2	4		T3	7950		T30	501
valid_sources[0x73]	3626017	1			T2	1		T3	7772		T30	621
valid_sources[0x74]	1336042	1			T2	3		T3	7760		T30	604
valid_sources[0x75]	1765262	1			T2	6		T3	7815		T30	782
valid_sources[0x76]	1299563	1			T3	7662		T8	71		T30	542
valid_sources[0x77]	1305287	1			T2	4		T3	7834		T30	547
valid_sources[0x78]	1298714	1			T2	13		T3	7625		T30	583
valid_sources[0x79]	1301902	1			T3	7609		T30	1595		T32	90
valid_sources[0x7a]	3257858	1			T2	7		T3	7591		T30	531
valid_sources[0x7b]	2169497	1			T1	1		T2	6		T3	7625
valid_sources[0x7c]	1295084	1			T3	7745		T30	1119		T32	61
valid_sources[0x7d]	1299043	1			T2	1		T3	7675		T30	589
valid_sources[0x7e]	1304164	1			T2	3		T3	7591		T30	574
valid_sources[0x7f]	1302657	1			T3	7704		T30	657		T32	66
valid_sources[0x80]	1354718	1			T2	3		T3	7603		T30	498

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71656828

1

T2

28

T3

322685

T7

320181

values[0x0]

all_enables

biggest_size

61065873

1

T1

2

T2

422

T3

261117

values[0x1]

all_enables

biggest_size

52637791

1

T2

393

T3

222029

T7

224474