Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262419830

1

T1

24

T2

79

T3

117043

full_word

185517141

1

T1

2

T2

843

T3

805831

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	447936671	1			T1	26		T2	922		T3	197627
auto[TlIntgErrCmd]	108	1			T118	3		T119	3		T120	7
auto[TlIntgErrData]	99	1			T118	4		T119	3		T120	5
auto[TlIntgErrBoth]	93	1			T118	3		T119	4		T120	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231473324

1

T1

1

T2

65

T3

103454

auto[1]

216463647

1

T1

25

T2

857

T3

941723

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159777321	1			T1	1		T2	37		T3	711862
auto[TlIntgErrNone]	partial	auto[1]	102642230	1			T1	23		T2	42		T3	458577
auto[TlIntgErrNone]	full_word	auto[0]	71695872	1			T2	28		T3	322685		T7	320181
auto[TlIntgErrNone]	full_word	auto[1]	113821248	1			T1	2		T2	815		T3	483146
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T119	1		T120	2		T176	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T118	3		T119	2		T120	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T177	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T176	1		T153	1		T178	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T118	2		T119	1		T120	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T118	2		T119	2		T120	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T175	1		T179	1		T153	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T175	1		T180	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T118	2		T119	3		T120	3
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T118	1		T119	1		T120	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T176	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T120	1		T176	1		T175	1