Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263261562

1

T1

625883

T2

6

T3

406945

full_word

186067152

1

T1

615846

T2

57

T3

250221

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	449328424	1			T1	124172		T2	63		T3	657166
auto[TlIntgErrCmd]	103	1			T116	7		T117	8		T118	4
auto[TlIntgErrData]	90	1			T116	7		T117	7		T118	2
auto[TlIntgErrBoth]	97	1			T116	6		T117	5		T118	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231880485

1

T1

629454

T2

5

T3

330967

auto[1]

217448229

1

T1

612275

T2

58

T3

326199

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159542809	1			T1	385434		T2	2		T3	242244
auto[TlIntgErrNone]	partial	auto[1]	103718487	1			T1	240449		T2	4		T3	164701
auto[TlIntgErrNone]	full_word	auto[0]	72337553	1			T1	244020		T2	3		T3	88723
auto[TlIntgErrNone]	full_word	auto[1]	113729575	1			T1	371826		T2	54		T3	161498
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T116	2		T117	4		T118	1
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T116	4		T117	4		T118	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T116	1		T174	1		T175	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T176	1		T177	1		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1			T116	2		T117	3		T118	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T116	4		T117	4		T118	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T116	1		T178	1		T179	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T178	1		T175	2		T180	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T116	2		T117	1		T118	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T116	4		T117	4		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T118	1		T181	1		T182	1