Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.67			87.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer.g_pos_dupcnt.u_pos	66.67			66.67
tb.dut.gen_entropy.u_entropy.u_hash_count	84.00			84.00
tb.dut.u_kmac_core.u_key_index_count	100.00			100.00
tb.dut.u_sha3.u_pad.u_sentmsg_count	100.00			100.00
tb.dut.u_sha3.u_keccak.u_round_count	100.00			100.00
tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr	100.00			100.00
tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr	100.00			100.00
tb.dut.gen_entropy.u_entropy.u_seed_idx_count	100.00			100.00

---

Module Instance : tb.dut.u_msgfifo.u_packer.g_pos_dupcnt.u_pos

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67			66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	100.00			92.31	100.00	u_packer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_entropy.u_entropy.u_hash_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_kmac_core.u_key_index_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.30	98.68	92.86		100.00	91.07	88.89	u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_pad.u_sentmsg_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	99.41	88.37		94.44	95.70	100.00	u_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_round_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.32	92.94	100.00		73.33	90.32	100.00	u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_entropy.u_entropy.u_seed_idx_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_kmac_core.u_key_index_count

SCORE	TOGGLE
100.00	100.00

tb.dut.u_sha3.u_pad.u_sentmsg_count

SCORE	TOGGLE
100.00	100.00

tb.dut.u_sha3.u_keccak.u_round_count

SCORE	TOGGLE
100.00	100.00

tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORE	TOGGLE
100.00	100.00

tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	9	9	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=10,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
84.00	84.00

tb.dut.gen_entropy.u_entropy.u_hash_count

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	50	42	84.00
Total Bits 0->1	25	21	84.00
Total Bits 1->0	25	21	84.00

Ports	7	5	71.43
Port Bits	50	42	84.00
Port Bits 0->1	25	21	84.00
Port Bits 1->0	25	21	84.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T9,T5	Yes	T1,T9,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[9:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[9:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[7:0]	Yes	Yes	*T1,*T4,*T10	Yes	T1,T4,T10	OUTPUT
cnt_o[9:8]	No	No		No		OUTPUT
cnt_after_commit_o[7:0]	Yes	Yes	*T1,*T4,*T10	Yes	T1,T4,T10	OUTPUT
cnt_after_commit_o[9:8]	No	No		No		OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

*Tests covering at least one bit in the range

---

Toggle Coverage for Module : prim_count ( parameter Width=8,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
66.67	66.67

tb.dut.u_msgfifo.u_packer.g_pos_dupcnt.u_pos

	Total	Covered	Percent
Totals	11	7	63.64
Total Bits	78	52	66.67
Total Bits 0->1	39	26	66.67
Total Bits 1->0	39	26	66.67

Ports	11	7	63.64
Port Bits	78	52	66.67
Port Bits 0->1	39	26	66.67
Port Bits 1->0	39	26	66.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	INPUT
set_cnt_i[2:0]	No	No		No		INPUT
set_cnt_i[7:3]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
step_i[2:0]	No	No		No		INPUT
step_i[6:3]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
step_i[7]	No	No		No		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	No	No		No		OUTPUT
cnt_o[7:3]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[2:0]	No	No		No		OUTPUT
cnt_after_commit_o[7:3]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_entropy.u_entropy.u_seed_idx_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.u_msgfifo.u_packer.g_pos_dupcnt.u_pos

	Total	Covered	Percent
Totals	11	7	63.64
Total Bits	78	52	66.67
Total Bits 0->1	39	26	66.67
Total Bits 1->0	39	26	66.67

Ports	11	7	63.64
Port Bits	78	52	66.67
Port Bits 0->1	39	26	66.67
Port Bits 1->0	39	26	66.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	INPUT
set_cnt_i[2:0]	No	No		No		INPUT
set_cnt_i[7:3]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
step_i[2:0]	No	No		No		INPUT
step_i[6:3]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
step_i[7]	No	No		No		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	No	No		No		OUTPUT
cnt_o[7:3]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[2:0]	No	No		No		OUTPUT
cnt_after_commit_o[7:3]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_hash_count

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	50	42	84.00
Total Bits 0->1	25	21	84.00
Total Bits 1->0	25	21	84.00

Ports	7	5	71.43
Port Bits	50	42	84.00
Port Bits 0->1	25	21	84.00
Port Bits 1->0	25	21	84.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T9,T5	Yes	T1,T9,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[9:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[9:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[7:0]	Yes	Yes	*T1,*T4,*T10	Yes	T1,T4,T10	OUTPUT
cnt_o[9:8]	No	No		No		OUTPUT
cnt_after_commit_o[7:0]	Yes	Yes	*T1,*T4,*T10	Yes	T1,T4,T10	OUTPUT
cnt_after_commit_o[9:8]	No	No		No		OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_kmac_core.u_key_index_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.u_sha3.u_pad.u_sentmsg_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.u_sha3.u_keccak.u_round_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	9	9	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	9	9	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_seed_idx_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT