Unified Coverage Report :: Module :: kmac_reg_top

Module : kmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.90	100.00	99.62			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.90	100.00	99.62			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.90	100.00	99.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.01	99.41	96.68	100.00		98.94	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.34	98.77	94.74	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault_err	100.00	100.00
u_alert_test_recov_operation_err	100.00	100.00
u_cfg_regwen	100.00	100.00
u_cfg_shadowed0_qe	100.00	100.00				100.00
u_cfg_shadowed_en_unsupported_modestrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_fast_process	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_ready	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_err_processed	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kmac_en	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kstrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_endianness	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_mask	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_sideload	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_state_endianness	98.66	100.00	94.64			100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_cmd	100.00	100.00
u_cmd_entropy_req	100.00	100.00
u_cmd_hash_cnt_clr	100.00	100.00
u_entropy_period_prescaler	100.00	100.00	100.00			100.00
u_entropy_period_wait_timer	100.00	100.00	100.00			100.00
u_entropy_refresh_hash_cnt	62.59	77.78	50.00			60.00
u_entropy_refresh_threshold_shadowed	98.66	100.00	94.64			100.00	100.00
u_entropy_seed_0	100.00	100.00
u_entropy_seed_1	100.00	100.00
u_entropy_seed_2	100.00	100.00
u_entropy_seed_3	100.00	100.00
u_entropy_seed_4	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_kmac_done	100.00	100.00	100.00			100.00
u_intr_enable_kmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	100.00	100.00	100.00			100.00
u_intr_state_kmac_done	100.00	100.00	100.00			100.00
u_intr_state_kmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_kmac_done	100.00	100.00
u_intr_test_kmac_err	100.00	100.00
u_key_len	100.00	100.00	100.00			100.00
u_key_share0_0	100.00	100.00
u_key_share0_1	100.00	100.00
u_key_share0_10	100.00	100.00
u_key_share0_11	100.00	100.00
u_key_share0_12	100.00	100.00
u_key_share0_13	100.00	100.00
u_key_share0_14	100.00	100.00
u_key_share0_15	100.00	100.00
u_key_share0_2	100.00	100.00
u_key_share0_3	100.00	100.00
u_key_share0_4	100.00	100.00
u_key_share0_5	100.00	100.00
u_key_share0_6	100.00	100.00
u_key_share0_7	100.00	100.00
u_key_share0_8	100.00	100.00
u_key_share0_9	100.00	100.00
u_key_share1_0	100.00	100.00
u_key_share1_1	100.00	100.00
u_key_share1_10	100.00	100.00
u_key_share1_11	100.00	100.00
u_key_share1_12	100.00	100.00
u_key_share1_13	100.00	100.00
u_key_share1_14	100.00	100.00
u_key_share1_15	100.00	100.00
u_key_share1_2	100.00	100.00
u_key_share1_3	100.00	100.00
u_key_share1_4	100.00	100.00
u_key_share1_5	100.00	100.00
u_key_share1_6	100.00	100.00
u_key_share1_7	100.00	100.00
u_key_share1_8	100.00	100.00
u_key_share1_9	100.00	100.00
u_prefix_0	100.00	100.00	100.00			100.00
u_prefix_1	100.00	100.00	100.00			100.00
u_prefix_10	100.00	100.00	100.00			100.00
u_prefix_2	100.00	100.00	100.00			100.00
u_prefix_3	100.00	100.00	100.00			100.00
u_prefix_4	100.00	100.00	100.00			100.00
u_prefix_5	100.00	100.00	100.00			100.00
u_prefix_6	100.00	100.00	100.00			100.00
u_prefix_7	100.00	100.00	100.00			100.00
u_prefix_8	100.00	100.00	100.00			100.00
u_prefix_9	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	91.58	96.18	82.65			87.50	100.00
u_status_alert_fatal_fault	100.00	100.00
u_status_alert_recov_ctrl_update_err	100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_status_sha3_absorb	100.00	100.00
u_status_sha3_idle	100.00	100.00
u_status_sha3_squeeze	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		528	528	100.00
ALWAYS	77	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
ALWAYS	136	3	3	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	606	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	786	1	1	100.00
CONT_ASSIGN	823	1	1	100.00
CONT_ASSIGN	860	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	934	1	1	100.00
CONT_ASSIGN	971	1	1	100.00
CONT_ASSIGN	1008	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1082	1	1	100.00
CONT_ASSIGN	1119	1	1	100.00
CONT_ASSIGN	1125	1	1	100.00
CONT_ASSIGN	1140	1	1	100.00
CONT_ASSIGN	1156	1	1	100.00
CONT_ASSIGN	1172	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1387	1	1	100.00
CONT_ASSIGN	1429	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1450	1	1	100.00
CONT_ASSIGN	1464	1	1	100.00
CONT_ASSIGN	1471	1	1	100.00
CONT_ASSIGN	1485	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1506	1	1	100.00
CONT_ASSIGN	1513	1	1	100.00
CONT_ASSIGN	1527	1	1	100.00
CONT_ASSIGN	1534	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1551	1	1	100.00
CONT_ASSIGN	1558	1	1	100.00
CONT_ASSIGN	1561	1	1	100.00
CONT_ASSIGN	1575	1	1	100.00
CONT_ASSIGN	1582	1	1	100.00
CONT_ASSIGN	1585	1	1	100.00
CONT_ASSIGN	1599	1	1	100.00
CONT_ASSIGN	1606	1	1	100.00
CONT_ASSIGN	1609	1	1	100.00
CONT_ASSIGN	1623	1	1	100.00
CONT_ASSIGN	1630	1	1	100.00
CONT_ASSIGN	1633	1	1	100.00
CONT_ASSIGN	1647	1	1	100.00
CONT_ASSIGN	1654	1	1	100.00
CONT_ASSIGN	1657	1	1	100.00
CONT_ASSIGN	1671	1	1	100.00
CONT_ASSIGN	1678	1	1	100.00
CONT_ASSIGN	1681	1	1	100.00
CONT_ASSIGN	1695	1	1	100.00
CONT_ASSIGN	1702	1	1	100.00
CONT_ASSIGN	1705	1	1	100.00
CONT_ASSIGN	1719	1	1	100.00
CONT_ASSIGN	1726	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1743	1	1	100.00
CONT_ASSIGN	1750	1	1	100.00
CONT_ASSIGN	1753	1	1	100.00
CONT_ASSIGN	1767	1	1	100.00
CONT_ASSIGN	1774	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1791	1	1	100.00
CONT_ASSIGN	1798	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1815	1	1	100.00
CONT_ASSIGN	1822	1	1	100.00
CONT_ASSIGN	1825	1	1	100.00
CONT_ASSIGN	1839	1	1	100.00
CONT_ASSIGN	1846	1	1	100.00
CONT_ASSIGN	1849	1	1	100.00
CONT_ASSIGN	1863	1	1	100.00
CONT_ASSIGN	1870	1	1	100.00
CONT_ASSIGN	1873	1	1	100.00
CONT_ASSIGN	1887	1	1	100.00
CONT_ASSIGN	1894	1	1	100.00
CONT_ASSIGN	1897	1	1	100.00
CONT_ASSIGN	1911	1	1	100.00
CONT_ASSIGN	1918	1	1	100.00
CONT_ASSIGN	1921	1	1	100.00
CONT_ASSIGN	1935	1	1	100.00
CONT_ASSIGN	1942	1	1	100.00
CONT_ASSIGN	1945	1	1	100.00
CONT_ASSIGN	1959	1	1	100.00
CONT_ASSIGN	1966	1	1	100.00
CONT_ASSIGN	1969	1	1	100.00
CONT_ASSIGN	1983	1	1	100.00
CONT_ASSIGN	1990	1	1	100.00
CONT_ASSIGN	1993	1	1	100.00
CONT_ASSIGN	2007	1	1	100.00
CONT_ASSIGN	2014	1	1	100.00
CONT_ASSIGN	2017	1	1	100.00
CONT_ASSIGN	2031	1	1	100.00
CONT_ASSIGN	2038	1	1	100.00
CONT_ASSIGN	2041	1	1	100.00
CONT_ASSIGN	2055	1	1	100.00
CONT_ASSIGN	2062	1	1	100.00
CONT_ASSIGN	2065	1	1	100.00
CONT_ASSIGN	2079	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00
CONT_ASSIGN	2089	1	1	100.00
CONT_ASSIGN	2103	1	1	100.00
CONT_ASSIGN	2110	1	1	100.00
CONT_ASSIGN	2113	1	1	100.00
CONT_ASSIGN	2127	1	1	100.00
CONT_ASSIGN	2134	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2151	1	1	100.00
CONT_ASSIGN	2158	1	1	100.00
CONT_ASSIGN	2161	1	1	100.00
CONT_ASSIGN	2175	1	1	100.00
CONT_ASSIGN	2182	1	1	100.00
CONT_ASSIGN	2185	1	1	100.00
CONT_ASSIGN	2199	1	1	100.00
CONT_ASSIGN	2206	1	1	100.00
CONT_ASSIGN	2209	1	1	100.00
CONT_ASSIGN	2223	1	1	100.00
CONT_ASSIGN	2230	1	1	100.00
CONT_ASSIGN	2233	1	1	100.00
CONT_ASSIGN	2247	1	1	100.00
CONT_ASSIGN	2254	1	1	100.00
CONT_ASSIGN	2257	1	1	100.00
CONT_ASSIGN	2271	1	1	100.00
CONT_ASSIGN	2278	1	1	100.00
CONT_ASSIGN	2281	1	1	100.00
CONT_ASSIGN	2295	1	1	100.00
CONT_ASSIGN	2301	1	1	100.00
CONT_ASSIGN	2333	1	1	100.00
CONT_ASSIGN	2365	1	1	100.00
CONT_ASSIGN	2397	1	1	100.00
CONT_ASSIGN	2429	1	1	100.00
CONT_ASSIGN	2461	1	1	100.00
CONT_ASSIGN	2493	1	1	100.00
CONT_ASSIGN	2525	1	1	100.00
CONT_ASSIGN	2557	1	1	100.00
CONT_ASSIGN	2589	1	1	100.00
CONT_ASSIGN	2621	1	1	100.00
CONT_ASSIGN	2653	1	1	100.00
ALWAYS	2712	62	62	100.00
CONT_ASSIGN	2776	1	1	100.00
ALWAYS	2780	1	1	100.00
CONT_ASSIGN	2845	1	1	100.00
CONT_ASSIGN	2847	1	1	100.00
CONT_ASSIGN	2849	1	1	100.00
CONT_ASSIGN	2851	1	1	100.00
CONT_ASSIGN	2852	1	1	100.00
CONT_ASSIGN	2854	1	1	100.00
CONT_ASSIGN	2856	1	1	100.00
CONT_ASSIGN	2858	1	1	100.00
CONT_ASSIGN	2859	1	1	100.00
CONT_ASSIGN	2861	1	1	100.00
CONT_ASSIGN	2863	1	1	100.00
CONT_ASSIGN	2865	1	1	100.00
CONT_ASSIGN	2866	1	1	100.00
CONT_ASSIGN	2868	1	1	100.00
CONT_ASSIGN	2870	1	1	100.00
CONT_ASSIGN	2871	1	1	100.00
CONT_ASSIGN	2872	1	1	100.00
CONT_ASSIGN	2873	1	1	100.00
CONT_ASSIGN	2875	1	1	100.00
CONT_ASSIGN	2877	1	1	100.00
CONT_ASSIGN	2879	1	1	100.00
CONT_ASSIGN	2881	1	1	100.00
CONT_ASSIGN	2883	1	1	100.00
CONT_ASSIGN	2885	1	1	100.00
CONT_ASSIGN	2887	1	1	100.00
CONT_ASSIGN	2889	1	1	100.00
CONT_ASSIGN	2891	1	1	100.00
CONT_ASSIGN	2893	1	1	100.00
CONT_ASSIGN	2895	1	1	100.00
CONT_ASSIGN	2897	1	1	100.00
CONT_ASSIGN	2898	1	1	100.00
CONT_ASSIGN	2900	1	1	100.00
CONT_ASSIGN	2902	1	1	100.00
CONT_ASSIGN	2904	1	1	100.00
CONT_ASSIGN	2905	1	1	100.00
CONT_ASSIGN	2906	1	1	100.00
CONT_ASSIGN	2908	1	1	100.00
CONT_ASSIGN	2910	1	1	100.00
CONT_ASSIGN	2911	1	1	100.00
CONT_ASSIGN	2912	1	1	100.00
CONT_ASSIGN	2914	1	1	100.00
CONT_ASSIGN	2915	1	1	100.00
CONT_ASSIGN	2917	1	1	100.00
CONT_ASSIGN	2918	1	1	100.00
CONT_ASSIGN	2920	1	1	100.00
CONT_ASSIGN	2921	1	1	100.00
CONT_ASSIGN	2923	1	1	100.00
CONT_ASSIGN	2924	1	1	100.00
CONT_ASSIGN	2926	1	1	100.00
CONT_ASSIGN	2927	1	1	100.00
CONT_ASSIGN	2929	1	1	100.00
CONT_ASSIGN	2930	1	1	100.00
CONT_ASSIGN	2932	1	1	100.00
CONT_ASSIGN	2933	1	1	100.00
CONT_ASSIGN	2935	1	1	100.00
CONT_ASSIGN	2936	1	1	100.00
CONT_ASSIGN	2938	1	1	100.00
CONT_ASSIGN	2939	1	1	100.00
CONT_ASSIGN	2941	1	1	100.00
CONT_ASSIGN	2942	1	1	100.00
CONT_ASSIGN	2944	1	1	100.00
CONT_ASSIGN	2945	1	1	100.00
CONT_ASSIGN	2947	1	1	100.00
CONT_ASSIGN	2948	1	1	100.00
CONT_ASSIGN	2950	1	1	100.00
CONT_ASSIGN	2951	1	1	100.00
CONT_ASSIGN	2953	1	1	100.00
CONT_ASSIGN	2954	1	1	100.00
CONT_ASSIGN	2956	1	1	100.00
CONT_ASSIGN	2957	1	1	100.00
CONT_ASSIGN	2959	1	1	100.00
CONT_ASSIGN	2960	1	1	100.00
CONT_ASSIGN	2962	1	1	100.00
CONT_ASSIGN	2963	1	1	100.00
CONT_ASSIGN	2965	1	1	100.00
CONT_ASSIGN	2966	1	1	100.00
CONT_ASSIGN	2968	1	1	100.00
CONT_ASSIGN	2969	1	1	100.00
CONT_ASSIGN	2971	1	1	100.00
CONT_ASSIGN	2972	1	1	100.00
CONT_ASSIGN	2974	1	1	100.00
CONT_ASSIGN	2975	1	1	100.00
CONT_ASSIGN	2977	1	1	100.00
CONT_ASSIGN	2978	1	1	100.00
CONT_ASSIGN	2980	1	1	100.00
CONT_ASSIGN	2981	1	1	100.00
CONT_ASSIGN	2983	1	1	100.00
CONT_ASSIGN	2984	1	1	100.00
CONT_ASSIGN	2986	1	1	100.00
CONT_ASSIGN	2987	1	1	100.00
CONT_ASSIGN	2989	1	1	100.00
CONT_ASSIGN	2990	1	1	100.00
CONT_ASSIGN	2992	1	1	100.00
CONT_ASSIGN	2993	1	1	100.00
CONT_ASSIGN	2995	1	1	100.00
CONT_ASSIGN	2996	1	1	100.00
CONT_ASSIGN	2998	1	1	100.00
CONT_ASSIGN	2999	1	1	100.00
CONT_ASSIGN	3001	1	1	100.00
CONT_ASSIGN	3002	1	1	100.00
CONT_ASSIGN	3004	1	1	100.00
CONT_ASSIGN	3005	1	1	100.00
CONT_ASSIGN	3007	1	1	100.00
CONT_ASSIGN	3008	1	1	100.00
CONT_ASSIGN	3010	1	1	100.00
CONT_ASSIGN	3011	1	1	100.00
CONT_ASSIGN	3013	1	1	100.00
CONT_ASSIGN	3014	1	1	100.00
CONT_ASSIGN	3016	1	1	100.00
CONT_ASSIGN	3017	1	1	100.00
CONT_ASSIGN	3019	1	1	100.00
CONT_ASSIGN	3020	1	1	100.00
CONT_ASSIGN	3022	1	1	100.00
CONT_ASSIGN	3023	1	1	100.00
CONT_ASSIGN	3025	1	1	100.00
CONT_ASSIGN	3026	1	1	100.00
CONT_ASSIGN	3028	1	1	100.00
CONT_ASSIGN	3029	1	1	100.00
CONT_ASSIGN	3031	1	1	100.00
CONT_ASSIGN	3032	1	1	100.00
CONT_ASSIGN	3034	1	1	100.00
CONT_ASSIGN	3035	1	1	100.00
CONT_ASSIGN	3037	1	1	100.00
CONT_ASSIGN	3038	1	1	100.00
CONT_ASSIGN	3040	1	1	100.00
CONT_ASSIGN	3041	1	1	100.00
CONT_ASSIGN	3043	1	1	100.00
CONT_ASSIGN	3044	1	1	100.00
CONT_ASSIGN	3046	1	1	100.00
CONT_ASSIGN	3047	1	1	100.00
CONT_ASSIGN	3049	1	1	100.00
CONT_ASSIGN	3050	1	1	100.00
CONT_ASSIGN	3052	1	1	100.00
CONT_ASSIGN	3053	1	1	100.00
CONT_ASSIGN	3055	1	1	100.00
CONT_ASSIGN	3056	1	1	100.00
CONT_ASSIGN	3058	1	1	100.00
CONT_ASSIGN	3059	1	1	100.00
CONT_ASSIGN	3061	1	1	100.00
ALWAYS	3065	62	62	100.00
ALWAYS	3131	91	91	100.00
ALWAYS	3416	3	3	100.00
ALWAYS	3424	3	3	100.00
CONT_ASSIGN	3432	1	1	100.00
CONT_ASSIGN	3435	1	1	100.00
CONT_ASSIGN	3450	1	1	100.00
CONT_ASSIGN	3467	1	1	100.00
CONT_ASSIGN	3475	1	1	100.00
CONT_ASSIGN	3476	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
77	1	1
78	1	1
79	1	1
80	1	1
			MISSING_ELSE
86	1	1
104	1	1
105	1	1
107	1	1
108	1	1
109	1	1
110	1	1
136	1	1
143	1	1
144	1	1
			MISSING_ELSE
174	1	1
175	1	1
559	1	1
574	1	1
590	1	1
606	1	1
612	1	1
627	1	1
643	1	1
676	1	1
712	1	1
749	1	1
786	1	1
823	1	1
860	1	1
897	1	1
934	1	1
971	1	1
1008	1	1
1045	1	1
1082	1	1
1119	1	1
1125	1	1
1140	1	1
1156	1	1
1172	1	1
1300	1	1
1387	1	1
1429	1	1
1443	1	1
1450	1	1
1464	1	1
1471	1	1
1485	1	1
1492	1	1
1506	1	1
1513	1	1
1527	1	1
1534	1	1
1537	1	1
1551	1	1
1558	1	1
1561	1	1
1575	1	1
1582	1	1
1585	1	1
1599	1	1
1606	1	1
1609	1	1
1623	1	1
1630	1	1
1633	1	1
1647	1	1
1654	1	1
1657	1	1
1671	1	1
1678	1	1
1681	1	1
1695	1	1
1702	1	1
1705	1	1
1719	1	1
1726	1	1
1729	1	1
1743	1	1
1750	1	1
1753	1	1
1767	1	1
1774	1	1
1777	1	1
1791	1	1
1798	1	1
1801	1	1
1815	1	1
1822	1	1
1825	1	1
1839	1	1
1846	1	1
1849	1	1
1863	1	1
1870	1	1
1873	1	1
1887	1	1
1894	1	1
1897	1	1
1911	1	1
1918	1	1
1921	1	1
1935	1	1
1942	1	1
1945	1	1
1959	1	1
1966	1	1
1969	1	1
1983	1	1
1990	1	1
1993	1	1
2007	1	1
2014	1	1
2017	1	1
2031	1	1
2038	1	1
2041	1	1
2055	1	1
2062	1	1
2065	1	1
2079	1	1
2086	1	1
2089	1	1
2103	1	1
2110	1	1
2113	1	1
2127	1	1
2134	1	1
2137	1	1
2151	1	1
2158	1	1
2161	1	1
2175	1	1
2182	1	1
2185	1	1
2199	1	1
2206	1	1
2209	1	1
2223	1	1
2230	1	1
2233	1	1
2247	1	1
2254	1	1
2257	1	1
2271	1	1
2278	1	1
2281	1	1
2295	1	1
2301	1	1
2333	1	1
2365	1	1
2397	1	1
2429	1	1
2461	1	1
2493	1	1
2525	1	1
2557	1	1
2589	1	1
2621	1	1
2653	1	1
2712	1	1
2713	1	1
2714	1	1
2715	1	1
2716	1	1
2717	1	1
2718	1	1
2719	1	1
2720	1	1
2721	1	1
2722	1	1
2723	1	1
2724	1	1
2725	1	1
2726	1	1
2727	1	1
2728	1	1
2729	1	1
2730	1	1
2731	1	1
2732	1	1
2733	1	1
2734	1	1
2735	1	1
2736	1	1
2737	1	1
2738	1	1
2739	1	1
2740	1	1
2741	1	1
2742	1	1
2743	1	1
2744	1	1
2745	1	1
2746	1	1
2747	1	1
2748	1	1
2749	1	1
2750	1	1
2751	1	1
2752	1	1
2753	1	1
2754	1	1
2755	1	1
2756	1	1
2757	1	1
2758	1	1
2759	1	1
2760	1	1
2761	1	1
2762	1	1
2763	1	1
2764	1	1
2765	1	1
2766	1	1
2767	1	1
2768	1	1
2769	1	1
2770	1	1
2771	1	1
2772	1	1
2773	1	1
2776	1	1
2780	1	1
2845	1	1
2847	1	1
2849	1	1
2851	1	1
2852	1	1
2854	1	1
2856	1	1
2858	1	1
2859	1	1
2861	1	1
2863	1	1
2865	1	1
2866	1	1
2868	1	1
2870	1	1
2871	1	1
2872	1	1
2873	1	1
2875	1	1
2877	1	1
2879	1	1
2881	1	1
2883	1	1
2885	1	1
2887	1	1
2889	1	1
2891	1	1
2893	1	1
2895	1	1
2897	1	1
2898	1	1
2900	1	1
2902	1	1
2904	1	1
2905	1	1
2906	1	1
2908	1	1
2910	1	1
2911	1	1
2912	1	1
2914	1	1
2915	1	1
2917	1	1
2918	1	1
2920	1	1
2921	1	1
2923	1	1
2924	1	1
2926	1	1
2927	1	1
2929	1	1
2930	1	1
2932	1	1
2933	1	1
2935	1	1
2936	1	1
2938	1	1
2939	1	1
2941	1	1
2942	1	1
2944	1	1
2945	1	1
2947	1	1
2948	1	1
2950	1	1
2951	1	1
2953	1	1
2954	1	1
2956	1	1
2957	1	1
2959	1	1
2960	1	1
2962	1	1
2963	1	1
2965	1	1
2966	1	1
2968	1	1
2969	1	1
2971	1	1
2972	1	1
2974	1	1
2975	1	1
2977	1	1
2978	1	1
2980	1	1
2981	1	1
2983	1	1
2984	1	1
2986	1	1
2987	1	1
2989	1	1
2990	1	1
2992	1	1
2993	1	1
2995	1	1
2996	1	1
2998	1	1
2999	1	1
3001	1	1
3002	1	1
3004	1	1
3005	1	1
3007	1	1
3008	1	1
3010	1	1
3011	1	1
3013	1	1
3014	1	1
3016	1	1
3017	1	1
3019	1	1
3020	1	1
3022	1	1
3023	1	1
3025	1	1
3026	1	1
3028	1	1
3029	1	1
3031	1	1
3032	1	1
3034	1	1
3035	1	1
3037	1	1
3038	1	1
3040	1	1
3041	1	1
3043	1	1
3044	1	1
3046	1	1
3047	1	1
3049	1	1
3050	1	1
3052	1	1
3053	1	1
3055	1	1
3056	1	1
3058	1	1
3059	1	1
3061	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3078	1	1
3079	1	1
3080	1	1
3081	1	1
3082	1	1
3083	1	1
3084	1	1
3085	1	1
3086	1	1
3087	1	1
3088	1	1
3089	1	1
3090	1	1
3091	1	1
3092	1	1
3093	1	1
3094	1	1
3095	1	1
3096	1	1
3097	1	1
3098	1	1
3099	1	1
3100	1	1
3101	1	1
3102	1	1
3103	1	1
3104	1	1
3105	1	1
3106	1	1
3107	1	1
3108	1	1
3109	1	1
3110	1	1
3111	1	1
3112	1	1
3113	1	1
3114	1	1
3115	1	1
3116	1	1
3117	1	1
3118	1	1
3119	1	1
3120	1	1
3121	1	1
3122	1	1
3123	1	1
3124	1	1
3125	1	1
3126	1	1
3131	1	1
3132	1	1
3134	1	1
3135	1	1
3136	1	1
3140	1	1
3141	1	1
3142	1	1
3146	1	1
3147	1	1
3148	1	1
3152	1	1
3153	1	1
3157	1	1
3161	1	1
3162	1	1
3163	1	1
3164	1	1
3165	1	1
3166	1	1
3167	1	1
3168	1	1
3169	1	1
3170	1	1
3171	1	1
3172	1	1
3176	1	1
3177	1	1
3178	1	1
3182	1	1
3183	1	1
3184	1	1
3185	1	1
3186	1	1
3187	1	1
3188	1	1
3189	1	1
3193	1	1
3194	1	1
3198	1	1
3202	1	1
3206	1	1
3210	1	1
3214	1	1
3218	1	1
3222	1	1
3226	1	1
3230	1	1
3234	1	1
3238	1	1
3242	1	1
3246	1	1
3250	1	1
3254	1	1
3258	1	1
3262	1	1
3266	1	1
3270	1	1
3274	1	1
3278	1	1
3282	1	1
3286	1	1
3290	1	1
3294	1	1
3298	1	1
3302	1	1
3306	1	1
3310	1	1
3314	1	1
3318	1	1
3322	1	1
3326	1	1
3330	1	1
3334	1	1
3338	1	1
3342	1	1
3346	1	1
3350	1	1
3354	1	1
3358	1	1
3362	1	1
3366	1	1
3370	1	1
3374	1	1
3378	1	1
3382	1	1
3386	1	1
3390	1	1
3394	1	1
3398	1	1
3402	1	1
3416	1	1
3417	1	1
3419	1	1
3424	1	1
3425	1	1
3427	1	1
3432	1	1
3435	1	1
3450	1	1
3467	1	1
3475	1	1
3476	1	1

---

Cond Coverage for Module : kmac_reg_top

	Total	Covered	Percent
Conditions	781	778	99.62
Logical	781	778	99.62
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
67-2780	100.00
2780-3432	99.17

---

Branch Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
Branches		76	76	100.00
TERNARY	2776	2	2	100.00
IF	77	3	3	100.00
TERNARY	136	3	3	100.00
IF	143	2	2	100.00
CASE	3132	62	62	100.00
IF	3416	2	2	100.00
IF	3424	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2776	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if ((!rst_ni))
-2-:	79	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	((tl_i.a_address[(AW - 1):0] inside {[1024:1535]})) ? 
-2-:	136	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T116,T117,T118
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3132	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
addr_hit[57]	Covered	T1,T2,T3
addr_hit[58]	Covered	T1,T2,T3
addr_hit[59]	Covered	T1,T2,T3
addr_hit[60]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3416	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3424	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	316459238	0	0
reAfterRv	2147483647	316459238	0	0
rePulse	2147483647	209406120	0	0
wePulse	2147483647	107053118	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	316459238	0	0
T1	130913	773611	0	0
T2	7101	63	0	0
T3	489928	488583	0	0
T4	626922	35174	0	0
T9	192598	10503	0	0
T10	123592	27649	0	0
T30	607308	174873	0	0
T31	150811	141634	0	0
T32	226133	142049	0	0
T35	22425	254	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	316459238	0	0
T1	130913	773611	0	0
T2	7101	63	0	0
T3	489928	488583	0	0
T4	626922	35174	0	0
T9	192598	10503	0	0
T10	123592	27649	0	0
T30	607308	174873	0	0
T31	150811	141634	0	0
T32	226133	142049	0	0
T35	22425	254	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	209406120	0	0
T1	130913	507418	0	0
T2	7101	5	0	0
T3	489928	323527	0	0
T4	626922	19613	0	0
T9	192598	6622	0	0
T10	123592	19337	0	0
T30	607308	114917	0	0
T31	150811	922939	0	0
T32	226133	924820	0	0
T35	22425	17	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107053118	0	0
T1	130913	266193	0	0
T2	7101	58	0	0
T3	489928	165056	0	0
T4	626922	15561	0	0
T9	192598	3881	0	0
T10	123592	8312	0	0
T30	607308	599560	0	0
T31	150811	493408	0	0
T32	226133	495672	0	0
T35	22425	237	0	0