Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.34	98.77	94.74	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	348513	0	0
RunThenComplete_M	2147483647	3068293	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348513	0	0
T1	130913	492	0	0
T2	7101	0	0	0
T3	489928	310	0	0
T4	626922	163	0	0
T9	192598	30	0	0
T10	123592	41	0	0
T30	607308	2337	0	0
T31	150811	2265	0	0
T32	226133	2265	0	0
T33	0	97	0	0
T34	0	2337	0	0
T35	22425	0	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3068293	0	0
T1	130913	9707	0	0
T2	7101	0	0	0
T3	489928	5462	0	0
T4	626922	589	0	0
T9	192598	148	0	0
T10	123592	220	0	0
T30	607308	13147	0	0
T31	150811	12979	0	0
T32	226133	12979	0	0
T33	0	3802	0	0
T34	0	13147	0	0
T35	22425	0	0	0