Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.34	98.77	94.74	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	534613	0	0
entropy_period_rd_A	2147483647	1362	0	0
intr_enable_rd_A	2147483647	1839	0	0
prefix_0_rd_A	2147483647	1274	0	0
prefix_10_rd_A	2147483647	1181	0	0
prefix_1_rd_A	2147483647	1238	0	0
prefix_2_rd_A	2147483647	1294	0	0
prefix_3_rd_A	2147483647	1292	0	0
prefix_4_rd_A	2147483647	1223	0	0
prefix_5_rd_A	2147483647	1218	0	0
prefix_6_rd_A	2147483647	1325	0	0
prefix_7_rd_A	2147483647	1274	0	0
prefix_8_rd_A	2147483647	1354	0	0
prefix_9_rd_A	2147483647	1352	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	534613	0	0
T54	725433	107446	0	0
T56	0	100025	0	0
T57	0	40875	0	0
T65	0	31610	0	0
T123	0	44430	0	0
T124	0	16493	0	0
T125	0	25674	0	0
T126	0	20857	0	0
T127	0	46138	0	0
T128	0	20172	0	0
T129	61213	0	0	0
T130	310168	0	0	0
T131	157756	0	0	0
T132	270309	0	0	0
T133	107979	0	0	0
T134	1320	0	0	0
T135	223981	0	0	0
T136	35565	0	0	0
T137	37083	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1362	0	0
T116	0	56	0	0
T118	0	55	0	0
T123	498729	47	0	0
T126	0	22	0	0
T150	0	134	0	0
T151	0	42	0	0
T152	0	17	0	0
T153	0	14	0	0
T154	0	7	0	0
T155	0	1	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1839	0	0
T90	0	1	0	0
T116	0	109	0	0
T120	0	5	0	0
T123	498729	48	0	0
T126	0	40	0	0
T150	0	151	0	0
T151	0	76	0	0
T152	0	17	0	0
T153	0	15	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0
T165	0	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1274	0	0
T90	0	1	0	0
T116	0	43	0	0
T118	0	47	0	0
T123	498729	39	0	0
T126	0	22	0	0
T150	0	126	0	0
T151	0	75	0	0
T152	0	10	0	0
T153	0	7	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0
T166	0	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1181	0	0
T90	0	3	0	0
T116	0	46	0	0
T118	0	45	0	0
T123	498729	32	0	0
T126	0	28	0	0
T150	0	92	0	0
T151	0	54	0	0
T152	0	13	0	0
T153	0	9	0	0
T154	0	54	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1238	0	0
T90	0	5	0	0
T116	0	65	0	0
T118	0	39	0	0
T123	498729	39	0	0
T126	0	53	0	0
T150	0	116	0	0
T151	0	75	0	0
T152	0	5	0	0
T153	0	10	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0
T166	0	6	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1294	0	0
T90	0	4	0	0
T116	0	24	0	0
T118	0	44	0	0
T123	498729	57	0	0
T126	0	44	0	0
T150	0	111	0	0
T151	0	68	0	0
T152	0	5	0	0
T153	0	11	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0
T166	0	9	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1292	0	0
T90	0	4	0	0
T116	0	34	0	0
T118	0	46	0	0
T123	498729	59	0	0
T126	0	25	0	0
T150	0	124	0	0
T151	0	54	0	0
T152	0	13	0	0
T153	0	6	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0
T166	0	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1223	0	0
T90	0	1	0	0
T116	0	44	0	0
T118	0	49	0	0
T123	498729	40	0	0
T126	0	19	0	0
T150	0	113	0	0
T151	0	91	0	0
T152	0	5	0	0
T153	0	5	0	0
T154	0	8	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1218	0	0
T90	0	2	0	0
T116	0	37	0	0
T118	0	29	0	0
T123	498729	70	0	0
T126	0	15	0	0
T150	0	87	0	0
T151	0	46	0	0
T152	0	11	0	0
T153	0	5	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0
T166	0	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1325	0	0
T90	0	1	0	0
T116	0	56	0	0
T118	0	52	0	0
T123	498729	55	0	0
T126	0	19	0	0
T150	0	132	0	0
T151	0	30	0	0
T152	0	8	0	0
T153	0	4	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0
T166	0	5	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1274	0	0
T90	0	1	0	0
T116	0	45	0	0
T118	0	43	0	0
T123	498729	41	0	0
T126	0	38	0	0
T150	0	144	0	0
T151	0	84	0	0
T152	0	12	0	0
T153	0	4	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0
T166	0	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1354	0	0
T90	0	7	0	0
T116	0	57	0	0
T118	0	49	0	0
T123	498729	82	0	0
T126	0	34	0	0
T150	0	106	0	0
T151	0	63	0	0
T152	0	9	0	0
T153	0	1	0	0
T154	0	69	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1352	0	0
T90	0	6	0	0
T116	0	58	0	0
T118	0	31	0	0
T123	498729	86	0	0
T126	0	27	0	0
T150	0	104	0	0
T151	0	80	0	0
T152	0	7	0	0
T153	0	4	0	0
T154	0	55	0	0
T156	20817	0	0	0
T157	788991	0	0	0
T158	893002	0	0	0
T159	596646	0	0	0
T160	194767	0	0	0
T161	25096	0	0	0
T162	105371	0	0	0
T163	26549	0	0	0
T164	149806	0	0	0