Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181484 |
1 |
|
|
T1 |
827 |
|
T32 |
419 |
|
T50 |
3255 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
93693 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65593 |
1 |
|
|
T1 |
29 |
|
T32 |
413 |
|
T50 |
3204 |
seven_bytes |
3183 |
1 |
|
|
T1 |
14 |
|
T57 |
33 |
|
T73 |
40 |
six_bytes |
3186 |
1 |
|
|
T1 |
22 |
|
T57 |
36 |
|
T73 |
35 |
five_bytes |
3265 |
1 |
|
|
T1 |
20 |
|
T57 |
38 |
|
T73 |
46 |
four_bytes |
3084 |
1 |
|
|
T1 |
20 |
|
T57 |
21 |
|
T73 |
36 |
three_bytes |
3195 |
1 |
|
|
T1 |
21 |
|
T57 |
31 |
|
T73 |
36 |
two_bytes |
3129 |
1 |
|
|
T1 |
31 |
|
T57 |
42 |
|
T73 |
46 |
one_byte |
3156 |
1 |
|
|
T1 |
21 |
|
T57 |
42 |
|
T73 |
36 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
178076 |
1 |
|
|
T1 |
815 |
|
T32 |
407 |
|
T50 |
3153 |
auto[1] |
3408 |
1 |
|
|
T1 |
12 |
|
T32 |
12 |
|
T50 |
102 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181484 |
1 |
|
|
T1 |
827 |
|
T32 |
419 |
|
T50 |
3255 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181471 |
1 |
|
|
T1 |
827 |
|
T32 |
419 |
|
T50 |
3255 |
auto[1] |
13 |
1 |
|
|
T41 |
2 |
|
T76 |
1 |
|
T53 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1192 |
1 |
|
|
T1 |
1 |
|
T32 |
6 |
|
T50 |
51 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3408 |
1 |
|
|
T1 |
12 |
|
T32 |
12 |
|
T50 |
102 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176163 |
1 |
|
|
T1 |
1585 |
|
T32 |
110 |
|
T50 |
3150 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
91369 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62991 |
1 |
|
|
T1 |
103 |
|
T32 |
108 |
|
T50 |
3104 |
seven_bytes |
3115 |
1 |
|
|
T1 |
53 |
|
T57 |
37 |
|
T73 |
40 |
six_bytes |
3179 |
1 |
|
|
T1 |
41 |
|
T57 |
23 |
|
T73 |
40 |
five_bytes |
3116 |
1 |
|
|
T1 |
41 |
|
T57 |
32 |
|
T73 |
36 |
four_bytes |
3053 |
1 |
|
|
T1 |
48 |
|
T57 |
30 |
|
T73 |
29 |
three_bytes |
3111 |
1 |
|
|
T1 |
41 |
|
T57 |
24 |
|
T73 |
51 |
two_bytes |
3090 |
1 |
|
|
T1 |
42 |
|
T57 |
34 |
|
T73 |
33 |
one_byte |
3139 |
1 |
|
|
T1 |
59 |
|
T57 |
29 |
|
T73 |
38 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172815 |
1 |
|
|
T1 |
1563 |
|
T32 |
106 |
|
T50 |
3058 |
auto[1] |
3348 |
1 |
|
|
T1 |
22 |
|
T32 |
4 |
|
T50 |
92 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176163 |
1 |
|
|
T1 |
1585 |
|
T32 |
110 |
|
T50 |
3150 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176154 |
1 |
|
|
T1 |
1585 |
|
T32 |
110 |
|
T50 |
3150 |
auto[1] |
9 |
1 |
|
|
T44 |
1 |
|
T167 |
1 |
|
T168 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1179 |
1 |
|
|
T1 |
5 |
|
T32 |
2 |
|
T50 |
46 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3348 |
1 |
|
|
T1 |
22 |
|
T32 |
4 |
|
T50 |
92 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350203 |
1 |
|
|
T1 |
2871 |
|
T32 |
1321 |
|
T50 |
5797 |
auto[1] |
542 |
1 |
|
|
T50 |
90 |
|
T53 |
41 |
|
T54 |
78 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
183352 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
123815 |
1 |
|
|
T1 |
111 |
|
T32 |
1301 |
|
T50 |
5797 |
seven_bytes |
6187 |
1 |
|
|
T1 |
83 |
|
T57 |
97 |
|
T73 |
38 |
six_bytes |
6218 |
1 |
|
|
T1 |
89 |
|
T57 |
86 |
|
T73 |
33 |
five_bytes |
6309 |
1 |
|
|
T1 |
74 |
|
T57 |
95 |
|
T73 |
34 |
four_bytes |
6321 |
1 |
|
|
T1 |
70 |
|
T57 |
60 |
|
T73 |
33 |
three_bytes |
6275 |
1 |
|
|
T1 |
64 |
|
T57 |
88 |
|
T73 |
40 |
two_bytes |
6146 |
1 |
|
|
T1 |
67 |
|
T57 |
77 |
|
T73 |
41 |
one_byte |
6122 |
1 |
|
|
T1 |
75 |
|
T57 |
84 |
|
T73 |
33 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
344064 |
1 |
|
|
T1 |
2827 |
|
T32 |
1281 |
|
T50 |
5707 |
auto[1] |
6681 |
1 |
|
|
T1 |
44 |
|
T32 |
40 |
|
T50 |
180 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350745 |
1 |
|
|
T1 |
2871 |
|
T32 |
1321 |
|
T50 |
5887 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350723 |
1 |
|
|
T1 |
2871 |
|
T32 |
1321 |
|
T50 |
5886 |
auto[1] |
22 |
1 |
|
|
T50 |
1 |
|
T53 |
1 |
|
T77 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2313 |
1 |
|
|
T1 |
9 |
|
T32 |
20 |
|
T50 |
90 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6681 |
1 |
|
|
T1 |
44 |
|
T32 |
40 |
|
T50 |
180 |