Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

265914971

1

T1

496071

T2

24

T3

586141

full_word

188012346

1

T1

396754

T2

5

T3

387140

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	453926997	1			T1	892825		T2	29		T3	973281
auto[TlIntgErrCmd]	103	1			T119	5		T120	6		T121	6
auto[TlIntgErrData]	119	1			T119	9		T120	6		T121	11
auto[TlIntgErrBoth]	98	1			T119	6		T120	8		T121	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233978813

1

T1

510598

T2

1

T3

519243

auto[1]

219948504

1

T1

382227

T2

28

T3

454038

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161393311	1			T1	337537		T2	1		T3	361503
auto[TlIntgErrNone]	partial	auto[1]	104521374	1			T1	158534		T2	23		T3	224638
auto[TlIntgErrNone]	full_word	auto[0]	72585357	1			T1	173061		T3	157740		T7	356
auto[TlIntgErrNone]	full_word	auto[1]	115426955	1			T1	223693		T2	5		T3	229400
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T120	2		T121	3		T176	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T119	4		T120	4		T121	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T119	1		T178	1		T179	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T176	1		T178	1		T177	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T119	5		T120	4		T121	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T119	2		T120	1		T121	7
auto[TlIntgErrData]	full_word	auto[0]	7	1			T119	1		T120	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T119	1		T180	2		T181	2
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T119	3		T120	3		T176	4
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T119	2		T120	3		T121	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T119	1		T120	1		T175	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T120	1		T182	1		T183	2