Unified Coverage Report :: Module

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_entropy.u_entropy.gen_lfsrs[0].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[1].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[2].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[3].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[4].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[5].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[6].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[7].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[8].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[9].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[10].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[11].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[12].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[13].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[14].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[15].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[16].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[17].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[18].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[19].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[20].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[21].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[22].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[23].u_lfsr_chunk	100.00			100.00
tb.dut.gen_entropy.u_entropy.gen_lfsrs[24].u_lfsr_chunk	100.00			100.00

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[0].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[1].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[2].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[3].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[4].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[5].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[6].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[7].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[8].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[9].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[10].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[11].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[12].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[13].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[14].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[15].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[16].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[17].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[18].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[19].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[20].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[21].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[22].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[23].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[24].u_lfsr_chunk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[0].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T28	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[1].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[2].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[3].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[4].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[5].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T28	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[6].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[7].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[8].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[9].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[10].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T28	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[11].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[12].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[13].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[14].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[15].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T28	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[16].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[17].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[18].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[19].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[20].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T28	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[21].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[22].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[23].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_entropy.u_entropy.gen_lfsrs[24].u_lfsr_chunk

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00


Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
seed_i[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lfsr_en_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT