Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	254065268	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

182407948

1

T1

1175

T2

12005

T3

399998

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	225952136	1			T1	757		T2	8669		T3	514973
values[0x0]	101184821	1			T1	561		T2	1953		T3	175005
values[0x1]	109336259	1			T1	543		T2	1929		T3	186135

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197410488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

239062728

1

T1

1337

T2

12153

T3

512939

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3269667	1			T1	15		T3	3418		T7	11
valid_sources[0x01]	1292635	1			T1	4		T3	3421		T7	6
valid_sources[0x02]	1301712	1			T1	4		T3	3337		T7	8
valid_sources[0x03]	1305875	1			T1	7		T3	3429		T7	3
valid_sources[0x04]	1306544	1			T1	7		T3	3391		T7	3
valid_sources[0x05]	1298924	1			T1	8		T3	3373		T7	8
valid_sources[0x06]	1306210	1			T1	7		T3	3403		T7	9
valid_sources[0x07]	1354269	1			T1	6		T3	3451		T7	6
valid_sources[0x08]	1295737	1			T1	6		T3	3436		T7	7
valid_sources[0x09]	1397613	1			T1	22		T3	3475		T7	7
valid_sources[0x0a]	1423523	1			T1	3		T2	12551		T3	3338
valid_sources[0x0b]	1301782	1			T1	3		T3	3405		T7	5
valid_sources[0x0c]	1307334	1			T1	6		T3	3399		T7	3
valid_sources[0x0d]	1490054	1			T1	2		T3	3451		T7	8
valid_sources[0x0e]	1303057	1			T1	2		T3	3409		T7	7
valid_sources[0x0f]	1397937	1			T3	3355		T7	4		T22	1
valid_sources[0x10]	1377323	1			T1	2		T3	3495		T7	12
valid_sources[0x11]	1296596	1			T1	8		T3	3309		T7	7
valid_sources[0x12]	1767248	1			T1	3		T3	3416		T7	5
valid_sources[0x13]	2177440	1			T1	7		T3	3405		T7	12
valid_sources[0x14]	1297862	1			T1	7		T3	3365		T7	4
valid_sources[0x15]	1308659	1			T1	5		T3	3490		T7	4
valid_sources[0x16]	1299152	1			T1	3		T3	3488		T7	7
valid_sources[0x17]	1301616	1			T1	14		T3	3455		T7	5
valid_sources[0x18]	1299446	1			T1	4		T3	3377		T7	8
valid_sources[0x19]	1299778	1			T1	12		T3	3626		T7	6
valid_sources[0x1a]	2361433	1			T1	5		T3	3354		T7	7
valid_sources[0x1b]	3265053	1			T1	13		T3	3423		T7	6
valid_sources[0x1c]	1303507	1			T1	4		T3	3507		T7	6
valid_sources[0x1d]	5103638	1			T1	3		T3	3455		T7	7
valid_sources[0x1e]	1309049	1			T1	4		T3	3443		T7	5
valid_sources[0x1f]	2201804	1			T1	14		T3	3405		T7	10
valid_sources[0x20]	1307774	1			T1	7		T3	3399		T7	11
valid_sources[0x21]	2293184	1			T1	22		T3	3523		T7	8
valid_sources[0x22]	1975548	1			T1	9		T3	3420		T7	10
valid_sources[0x23]	2327887	1			T3	3595		T7	8		T22	1
valid_sources[0x24]	2134140	1			T1	7		T3	3263		T7	7
valid_sources[0x25]	1308809	1			T1	4		T3	3523		T7	7
valid_sources[0x26]	1310731	1			T1	13		T3	3342		T7	4
valid_sources[0x27]	1295976	1			T1	3		T3	3477		T7	7
valid_sources[0x28]	1949036	1			T1	14		T3	3446		T7	6
valid_sources[0x29]	1296074	1			T1	3		T3	3368		T7	9
valid_sources[0x2a]	3607636	1			T1	4		T3	3386		T7	9
valid_sources[0x2b]	1295129	1			T1	2		T3	3467		T7	5
valid_sources[0x2c]	1306455	1			T1	5		T3	3425		T7	1
valid_sources[0x2d]	5592423	1			T1	3		T3	3429		T7	8
valid_sources[0x2e]	1305159	1			T1	6		T3	3388		T7	9
valid_sources[0x2f]	1370978	1			T1	34		T3	3464		T7	6
valid_sources[0x30]	1301229	1			T1	7		T3	3430		T7	8
valid_sources[0x31]	1307342	1			T1	5		T3	3432		T7	11
valid_sources[0x32]	3241100	1			T1	10		T3	3390		T7	1
valid_sources[0x33]	1739366	1			T1	1		T3	3374		T7	6
valid_sources[0x34]	1453860	1			T1	3		T3	3410		T7	6
valid_sources[0x35]	1583484	1			T1	7		T3	3497		T7	5
valid_sources[0x36]	1751839	1			T1	4		T3	3419		T7	9
valid_sources[0x37]	1299350	1			T1	5		T3	3508		T7	10
valid_sources[0x38]	1301101	1			T1	8		T3	3320		T7	3
valid_sources[0x39]	1298079	1			T1	5		T3	3430		T7	8
valid_sources[0x3a]	1942109	1			T3	3497		T7	3		T22	2
valid_sources[0x3b]	1309431	1			T1	4		T3	3425		T7	1
valid_sources[0x3c]	3626888	1			T1	11		T3	3512		T7	12
valid_sources[0x3d]	1356044	1			T1	3		T3	3363		T7	4
valid_sources[0x3e]	1302675	1			T1	3		T3	3399		T7	9
valid_sources[0x3f]	1299976	1			T1	8		T3	3450		T7	6
valid_sources[0x40]	1489715	1			T1	10		T3	3456		T7	7
valid_sources[0x41]	1309950	1			T1	2		T3	3281		T7	4
valid_sources[0x42]	1301074	1			T1	7		T3	3453		T7	9
valid_sources[0x43]	1306991	1			T1	11		T3	3466		T7	8
valid_sources[0x44]	2170308	1			T1	10		T3	3365		T7	6
valid_sources[0x45]	1306695	1			T1	6		T3	3481		T7	3
valid_sources[0x46]	1297412	1			T1	9		T3	3634		T22	2
valid_sources[0x47]	1963767	1			T1	13		T3	3402		T7	2
valid_sources[0x48]	1321961	1			T1	4		T3	3333		T7	4
valid_sources[0x49]	1302258	1			T1	14		T3	3440		T7	3
valid_sources[0x4a]	1382596	1			T1	15		T3	3484		T7	6
valid_sources[0x4b]	1339675	1			T1	5		T3	3366		T7	5
valid_sources[0x4c]	2103938	1			T1	12		T3	3496		T7	6
valid_sources[0x4d]	1304330	1			T1	15		T3	3465		T7	8
valid_sources[0x4e]	2190459	1			T1	6		T3	3440		T7	4
valid_sources[0x4f]	1298569	1			T1	23		T3	3319		T7	3
valid_sources[0x50]	1310782	1			T1	1		T3	3348		T7	8
valid_sources[0x51]	1296468	1			T1	3		T3	3379		T7	5
valid_sources[0x52]	1302418	1			T1	4		T3	3434		T7	8
valid_sources[0x53]	2030074	1			T1	5		T3	3345		T7	7
valid_sources[0x54]	1304935	1			T1	12		T3	3531		T7	6
valid_sources[0x55]	3666078	1			T1	22		T3	3403		T7	7
valid_sources[0x56]	1999883	1			T1	3		T3	3365		T7	8
valid_sources[0x57]	1310752	1			T1	7		T3	3500		T7	9
valid_sources[0x58]	1314084	1			T1	1		T3	3427		T7	7
valid_sources[0x59]	1298597	1			T3	3305		T7	4		T8	209
valid_sources[0x5a]	1306892	1			T1	6		T3	3487		T7	12
valid_sources[0x5b]	2265901	1			T1	11		T3	3421		T7	11
valid_sources[0x5c]	1304513	1			T1	1		T3	3393		T7	5
valid_sources[0x5d]	1302419	1			T1	6		T3	3446		T7	13
valid_sources[0x5e]	1301441	1			T1	7		T3	3529		T7	9
valid_sources[0x5f]	1310323	1			T1	14		T3	3500		T7	6
valid_sources[0x60]	1307335	1			T1	1		T3	3461		T7	5
valid_sources[0x61]	1303217	1			T3	3448		T7	5		T22	2
valid_sources[0x62]	1512194	1			T1	9		T3	3417		T7	8
valid_sources[0x63]	1300105	1			T1	3		T3	3412		T7	11
valid_sources[0x64]	1303296	1			T1	8		T3	3302		T7	5
valid_sources[0x65]	1307155	1			T1	12		T3	3488		T7	7
valid_sources[0x66]	1294554	1			T1	3		T3	3435		T7	5
valid_sources[0x67]	1301161	1			T1	4		T3	3247		T7	18
valid_sources[0x68]	2219999	1			T1	4		T3	3475		T7	4
valid_sources[0x69]	2092106	1			T1	18		T3	3506		T7	5
valid_sources[0x6a]	3868616	1			T1	13		T3	3329		T7	16
valid_sources[0x6b]	2119212	1			T1	2		T3	3416		T7	10
valid_sources[0x6c]	3311563	1			T1	17		T3	3506		T7	5
valid_sources[0x6d]	3651230	1			T1	5		T3	3351		T7	9
valid_sources[0x6e]	2080714	1			T1	17		T3	3484		T7	4
valid_sources[0x6f]	1300458	1			T1	2		T3	3286		T7	7
valid_sources[0x70]	1486270	1			T1	6		T3	3498		T7	9
valid_sources[0x71]	2143871	1			T1	9		T3	3291		T7	6
valid_sources[0x72]	1299962	1			T1	4		T3	3562		T7	4
valid_sources[0x73]	4125583	1			T1	5		T3	3389		T7	9
valid_sources[0x74]	2194381	1			T1	1		T3	3388		T7	4
valid_sources[0x75]	1315591	1			T3	3452		T7	5		T8	47
valid_sources[0x76]	2742488	1			T1	7		T3	3430		T7	9
valid_sources[0x77]	1310352	1			T3	3424		T7	4		T22	4
valid_sources[0x78]	3664739	1			T1	7		T3	3359		T7	10
valid_sources[0x79]	1844701	1			T1	8		T3	3497		T7	12
valid_sources[0x7a]	2208981	1			T1	13		T3	3513		T7	13
valid_sources[0x7b]	1299158	1			T1	5		T3	3457		T7	4
valid_sources[0x7c]	1299604	1			T1	6		T3	3372		T7	8
valid_sources[0x7d]	1302954	1			T1	4		T3	3376		T7	3
valid_sources[0x7e]	1296591	1			T1	8		T3	3412		T7	7
valid_sources[0x7f]	1295842	1			T1	3		T3	3471		T7	7
valid_sources[0x80]	2608563	1			T1	1		T3	3426		T7	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70366304

1

T1

357

T2

8404

T3

173479

values[0x0]

all_enables

biggest_size

60139385

1

T1

429

T2

1818

T3

118822

values[0x1]

all_enables

biggest_size

51902259

1

T1

389

T2

1783

T3

107697