Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256222930

1

T1

686

T2

546

T3

476115

full_word

182544164

1

T1

1175

T2

12005

T3

399998

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	438766804	1			T1	1861		T2	12551		T3	876113
auto[TlIntgErrCmd]	105	1			T122	3		T124	4		T177	10
auto[TlIntgErrData]	101	1			T122	8		T123	4		T124	5
auto[TlIntgErrBoth]	84	1			T122	9		T123	6		T124	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

226369186

1

T1

757

T2

8669

T3

514973

auto[1]

212397908

1

T1

1104

T2

3882

T3

361140

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	155968617	1			T1	400		T2	265		T3	341494
auto[TlIntgErrNone]	partial	auto[1]	100254045	1			T1	286		T2	281		T3	134621
auto[TlIntgErrNone]	full_word	auto[0]	70400445	1			T1	357		T2	8404		T3	173479
auto[TlIntgErrNone]	full_word	auto[1]	112143697	1			T1	818		T2	3601		T3	226519
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T124	1		T177	1		T154	3
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T122	3		T124	2		T177	8
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T180	1		T181	1		T182	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T124	1		T177	1		T155	2
auto[TlIntgErrData]	partial	auto[0]	52	1			T122	3		T123	2		T124	4
auto[TlIntgErrData]	partial	auto[1]	41	1			T122	5		T123	1		T124	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T180	1		T183	3		T184	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T123	1		T177	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T122	5		T123	2		T124	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T122	4		T123	3		T177	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T180	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T123	1		T181	2		T186	1